URL
https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk
Subversion Repositories sdhc-sc-core
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- This comparison shows the changes necessary to convert path
/sdhc-sc-core/trunk/src/grpCrc
- from Rev 164 to Rev 165
- ↔ Reverse comparison
Rev 164 → Rev 165
/unitCrc/src/Crc-Rtl-ea.vhdl
43,9 → 43,9
); |
port ( |
iClk : in std_ulogic; |
inResetAsync : in std_ulogic; -- Asynchronous low active reset |
iClear : in std_ulogic; -- Synchronous reset for the registers |
iRstSync : in std_ulogic; -- Synchronous high active reset |
iStrobe : in std_ulogic; -- Strobe, only shift when it is activated |
iClear : in std_ulogic; -- Clear register |
iDataIn : in std_ulogic; -- Signal that currently data is shifted in. |
-- Otherwise the current remainder is shifted out. |
iData : in std_ulogic; -- Data input |
69,15 → 69,13
begin |
|
-- shift registers |
crc : process (iClk, inResetAsync) is |
crc : process (iClk) is |
variable input : std_ulogic; |
begin |
if (inResetAsync = '0') then |
regs <= (others => '0'); |
elsif (rising_edge(iClk)) then |
if (iClear = '1') then |
if (rising_edge(iClk)) then |
if (iRstSync = '1') then |
regs <= (others => '0'); |
elsif (iClear = '0') then |
else |
if (iStrobe = '1') then |
if (iDataIn = '1') then |
-- calculate CRC |
99,6 → 97,10
regs(idx) <= regs(idx-1); |
end loop; |
end if; |
|
if (iClear = '1') then |
regs <= (others => '0'); |
end if; |
end if; |
end if; |
end if; |