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URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

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  • This comparison shows the changes necessary to convert path
    /sdhc-sc-core/trunk/src/grpSd/unitSdController
    from Rev 84 to Rev 85
    Reverse comparison

Rev 84 → Rev 85

/src/SdController-Rtl-ea.vhdl
28,7 → 28,7
 
architecture Rtl of SdController is
 
type aSdControllerState is (init, idle, invalidCard);
type aSdControllerState is (startup, init, idle, invalidCard);
type aCmdRegion is (CMD0, CMD8, CMD55, ACMD41, CMD2, CMD3);
type aRegion is (send, receive);
48,7 → 48,7
end record aSdControllerReg;
 
constant cDefaultSdControllerReg : aSdControllerReg := (
State => init,
State => startup,
CmdRegion => CMD0,
Region => send,
HCS => cActivated,
55,8 → 55,11
CCS => cInactivated,
RCA => cDefaultRCA);
 
signal R, NextR : aSdControllerReg;
 
signal R, NextR : aSdControllerReg;
signal TimeoutEnable : std_ulogic;
signal Timeout : std_ulogic;
 
begin
 
Regs : process (iClk, inResetAsync)
68,18 → 71,26
end if;
end process Regs;
 
Comb : process (iSdCmd, R)
Comb : process (iSdCmd, Timeout, R)
variable ocr : aSdRegOCR;
variable arg : aSdCmdArg;
begin
-- default assignments
oSdCmd <= cDefaultoSdCmd;
NextR <= R;
oSdCmd <= cDefaultoSdCmd;
NextR <= R;
TimeoutEnable <= cInactivated;
 
-- Status
oLedBank <= (others => cInactivated);
 
case R.State is
when startup =>
TimeoutEnable <= cActivated;
if (Timeout = cActivated) then
NextR.State <= init;
end if;
 
when init =>
case R.CmdRegion is
when CMD0 =>
89,10 → 100,17
oSdCmd.Valid <= cActivated;
 
if (iSdCmd.Ack = cActivated) then
NextR.Region <= receive;
end if;
 
when receive =>
TimeoutEnable <= cActivated;
 
if (Timeout = cActivated) then
NextR.Region <= send;
NextR.CmdRegion <= CMD8;
NextR.Region <= send;
end if;
 
when others =>
report "SdController: Unhandled state" severity error;
end case;
277,5 → 295,17
report "SdController: Unhandled state" severity error;
end case;
end process Comb;
 
TimeoutGenerator_inst: entity work.TimeoutGenerator
generic map (
gClkFrequency => 25E6,
gTimeoutTime => 100 ms
)
port map (
iClk => iClk,
inResetAsync => inResetAsync,
iEnable => TimeoutEnable,
oTimeout => Timeout);
 
end architecture Rtl;
 

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