URL
https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk
Subversion Repositories sdhc-sc-core
Compare Revisions
- This comparison shows the changes necessary to convert path
/sdhc-sc-core/trunk/src/grpSd/unitSdData
- from Rev 109 to Rev 110
- ↔ Reverse comparison
Rev 109 → Rev 110
/src/SdData-Rtl-a.vhdl
116,6 → 116,36
return (to_integer(word) * 8) + to_integer(byte); |
end function CalcBitAddrInWord; |
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procedure NextCounterAndSaveToRam(constant byteend : natural; constant bytedec : natural) is |
begin |
if (R.ByteCounter = byteend) then |
NextByteCounter := to_unsigned(7, aByteCounter'length); |
|
if (R.WordCounter = 0) then |
NextWordCounter := to_unsigned(3, aWordCounter'length); |
NextR.FirstSend <= cInactivated; |
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-- save word to ram |
NextR.Ram.We <= cActivated; |
NextR.Ram.En <= cActivated; |
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if (R.BlockCounter = 0) then |
NextRegion := crc; |
else |
NextBlockCounter := R.BlockCounter - 1; |
end if; |
else |
if (R.WordCounter = 3 and R.FirstSend = cInactivated) then |
NextRamAddr := R.Ram.Addr + 1; |
end if; |
|
NextWordCounter := R.WordCounter - 1; |
end if; |
else |
NextByteCounter := R.ByteCounter - bytedec; |
end if; |
end procedure NextCounterAndSaveToRam; |
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variable temp : std_ulogic_vector(3 downto 0); |
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begin |
251,63 → 281,15
when standard => |
NextR.Ram.Data(CalcBitAddrInWord(R.WordCounter, R.ByteCounter)) <= ioData(0); |
ShiftIntoCrc("000" & ioData(0)); |
NextCounterAndSaveToRam(0, 1); |
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if (R.ByteCounter = 0) then |
NextByteCounter := to_unsigned(7, aByteCounter'length); |
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if (R.WordCounter = 0) then |
NextWordCounter := to_unsigned(3, aWordCounter'length); |
NextR.FirstSend <= cInactivated; |
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-- save word to ram |
NextR.Ram.We <= cActivated; |
NextR.Ram.En <= cActivated; |
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if (R.BlockCounter = 0) then |
NextRegion := crc; |
else |
NextBlockCounter := R.BlockCounter - 1; |
end if; |
else |
if (R.WordCounter = 3 and R.FirstSend = cInactivated) then |
NextRamAddr := R.Ram.Addr + 1; |
end if; |
|
NextWordCounter := R.WordCounter - 1; |
end if; |
else |
NextByteCounter := R.ByteCounter - 1; |
end if; |
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when wide => |
for idx in 0 to 3 loop |
NextR.Ram.Data(CalcBitAddrInWord(R.WordCounter, R.ByteCounter - idx)) <= ioData(3 - idx); |
end loop; |
ShiftIntoCrc(std_ulogic_vector(ioData)); |
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if (R.ByteCounter = 3) then |
NextByteCounter := to_unsigned(7, aByteCounter'length); |
NextCounterAndSaveToRam(3, 4); |
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if (R.WordCounter = 0) then |
NextWordCounter := to_unsigned(3, aWordCounter'length); |
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-- save word to ram |
NextR.Ram.We <= cActivated; |
NextR.Ram.En <= cActivated; |
NextRamAddr := R.Ram.Addr + 1; |
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if (R.BlockCounter = 0) then |
NextRegion := crc; |
else |
NextBlockCounter := R.BlockCounter - 1; |
end if; |
else |
NextWordCounter := R.WordCounter - 1; |
end if; |
else |
NextByteCounter := R.ByteCounter - 4; |
end if; |
|
when others => |
report "Unhandled mode" severity error; |
end case; |