URL
https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk
Subversion Repositories sdhc-sc-core
Compare Revisions
- This comparison shows the changes necessary to convert path
/sdhc-sc-core/trunk/src/grpSd/unitSdData
- from Rev 164 to Rev 165
- ↔ Reverse comparison
Rev 164 → Rev 165
/src/SdData-Rtl-a.vhdl
64,13 → 64,11
DisableSdClk => cInactivated); |
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type aCrcOut is record |
Clear : std_ulogic; |
DataIn : std_ulogic; |
Data : std_ulogic_vector(3 downto 0); |
end record aCrcOut; |
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constant cDefaultCrcOut : aCrcOut := ( |
Clear => cInactivated, |
DataIn => cInactivated, |
Data => (others => '0')); |
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100,26 → 98,25
oDisableSdClk <= R.DisableSdClk; |
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Regs : process (iClk, inResetAsync) |
Regs : process (iClk) |
begin |
-- asynchronous reset |
if (inResetAsync = cnActivated) then |
R <= cDefaultReg; |
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-- clock event |
elsif (iClk'event and iClk = cActivated) then |
if (iClk'event and iClk = cActivated) then |
if (iRstSync = cActivated) then |
R <= cDefaultReg; |
else |
-- synchronous enable |
if (iStrobe = cActivated) then |
R <= NextR; |
end if; |
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-- synchronous enable |
if (iStrobe = cActivated) then |
R <= NextR; |
-- rdreq and wrreq have to be exactly one clock cycle wide |
R.ReadWriteFifo.rdreq <= NextR.ReadWriteFifo.rdreq and iStrobe; |
R.WriteReadFifo.wrreq <= NextR.WriteReadFifo.wrreq and iStrobe; |
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-- Clock has to be disabled before the next strobe is generated |
R.DisableSdClk <= NextR.DisableSdClk; |
end if; |
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-- rdreq and wrreq have to be exactly one clock cycle wide |
R.ReadWriteFifo.rdreq <= NextR.ReadWriteFifo.rdreq and iStrobe; |
R.WriteReadFifo.wrreq <= NextR.WriteReadFifo.wrreq and iStrobe; |
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-- Clock has to be disabled before the next strobe is generated |
R.DisableSdClk <= NextR.DisableSdClk; |
end if; |
end process Regs; |
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469,9 → 466,9
) |
port map ( |
iClk => iClk, |
inResetAsync => inResetAsync, |
iRstSync => iRstSync, |
iStrobe => iStrobe, |
iClear => CrcOut.Clear, |
iClear => cInactivated, |
iDataIn => CrcDataIn(idx), |
iData => CrcOut.Data(idx), |
oIsCorrect => CrcIn.Correct(idx), |
/src/SdData-e.vhdl
36,7 → 36,7
port ( |
-- clock |
iClk : in std_ulogic; |
inResetAsync : in std_ulogic; |
iRstSync : in std_ulogic; |
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iStrobe : in std_ulogic; |
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