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URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

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  • This comparison shows the changes necessary to convert path 
    /sdhc-sc-core/trunk/src/grpSd/unitSdTop/src
    from Rev 180 to Rev 182
    ↔ Reverse comparison
  •

Rev 180 → Rev 182

/SdTop-Rtl-ea.vhdl
82,25 → 82,21
 
architecture Rtl of SdTop is
 
signal iSdCtrl, oWbCtrl : aSdWbSlaveToSdController;
signal oSdCtrl, iWbCtrl : aSdControllerToSdWbSlave;
signal iSdWriteFifo : aiReadFifo;
signal oSdWriteFifo : aoReadFifo;
signal iSdReadFifo : aiWriteFifo;
signal oSdReadFifo : aoWriteFifo;
signal iWbWriteFifo : aiWriteFifo;
signal oWbWriteFifo : aoWriteFifo;
signal iWbReadFifo : aiReadFifo;
signal oWbReadFifo : aoReadFifo;
signal iSdCtrlSync : aSdWbSlaveToSdController;
signal oWbCtrl : aSdWbSlaveToSdController;
signal oSdCtrl : aSdControllerToSdWbSlave;
signal iWbCtrlSync : aSdControllerToSdWbSlave;
signal iSdWriteFifo : aiReadFifo;
signal oSdWriteFifo : aoReadFifo;
signal iSdReadFifo : aiWriteFifo;
signal oSdReadFifo : aoWriteFifo;
signal iWbWriteFifo : aiWriteFifo;
signal oWbWriteFifo : aoWriteFifo;
signal iWbReadFifo : aiReadFifo;
signal oWbReadFifo : aoReadFifo;
 
signal ReadFifoQTemp : std_logic_vector(31 downto 0);
signal WriteFifoQTemp : std_logic_vector(31 downto 0);
 
begin
 
--------------------------------------------------------------------------------
-- clk domains
--------------------------------------------------------------------------------
SdClkDomain_inst: entity work.SdClkDomain
generic map (
gClkFrequency => gClkFrequency,
114,7 → 110,7
ioData => ioData,
oLedBank => oLedBank,
oSdCtrl => oSdCtrl,
iSdCtrl => iSdCtrl,
iSdCtrl => iSdCtrlSync,
iSdWriteFifo => iSdWriteFifo,
oSdWriteFifo => oSdWriteFifo,
iSdReadFifo => iSdReadFifo,
143,53 → 139,31
oWriteFifo => oWbWriteFifo,
oReadFifo => oWbReadFifo,
oWbToSdCtrl => oWbCtrl,
iSdCtrlToWb => iWbCtrl
iSdCtrlToWb => iWbCtrlSync
);
 
--------------------------------------------------------------------------------
-- clk domain synchronization
--------------------------------------------------------------------------------
SdWbControllerSync_inst: entity work.SdWbControllerSync
SdWbClkDomainSync_inst: entity work.SdWbClkDomainSync
generic map (
gUseSameClocks => gUseSameClocks
)
port map (
iWbClk => iWbClk,
iWbRstSync => iWbRstSync,
iSdClk => iSdClk,
iSdRstSync => iSdRstSync,
iSdWb => oWbCtrl,
oSdWb => iWbCtrl,
iSdController => oSdCtrl,
oSdController => iSdCtrl
);
 
WriteDataFifo_inst: entity work.WriteDataFifo
port map (
data => std_logic_vector(oWbWriteFifo.data),
rdclk => iSdClk,
rdreq => oSdWriteFifo.rdreq,
wrclk => iWbClk,
wrreq => oWbWriteFifo.wrreq,
q => ReadFifoQTemp,
rdempty => iSdWriteFifo.rdempty,
wrfull => iWbWriteFifo.wrfull
);
iSdWriteFifo.q <= std_ulogic_vector(ReadFifoQTemp);
 
ReadDataFifo_inst: entity work.WriteDataFifo
port map (
data => std_logic_vector(oSdReadFifo.data),
rdclk => iWbClk,
rdreq => oWbReadFifo.rdreq,
wrclk => iSdClk,
wrreq => oSdReadFifo.wrreq,
q => WriteFifoQTemp,
rdempty => iWbReadFifo.rdempty,
wrfull => iSdReadFifo.wrfull
);
iWbReadFifo.q <= std_ulogic_vector(WriteFifoQTemp);
 
iWbClk => iWbClk,
iWbRstSync => iWbRstSync,
iSdClk => iSdClk,
iSdRstSync => iSdRstSync,
iWbCtrl => oWbCtrl,
iWbWriteFifo => oWbWriteFifo,
iWbReadFifo => oWbReadFifo,
iSdCtrl => oSdCtrl,
iSdWriteFifo => oSdWriteFifo,
iSdReadFifo => oSdReadFifo,
oWbCtrlSync => iWbCtrlSync,
oWbWriteFifo => iWbWriteFifo,
oWbReadFifo => iWbReadFifo,
oSdCtrlSync => iSdCtrlSync,
oSdWriteFifo => iSdWriteFifo,
oSdReadFifo => iSdReadFifo
);
end architecture Rtl;
 

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