URL
https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk
Subversion Repositories sdhc-sc-core
Compare Revisions
- This comparison shows the changes necessary to convert path
/sdhc-sc-core/trunk/src/grpSd/unitSdTop
- from Rev 122 to Rev 123
- ↔ Reverse comparison
Rev 122 → Rev 123
/src/SdTop-Rtl-ea.vhdl
66,19 → 66,21
signal SdControllerFromDataRam : aSdControllerFromRam; |
signal iSdWbSync, oSdControllerSync : aSdWbSlaveToSdController; |
signal iSdControllerSync, oSdWbSync : aSdControllerToSdWbSlave; |
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signal SdStrobe : std_ulogic; |
signal HighSpeed : std_ulogic; |
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signal iCmd : aiSdCmd; |
signal oCmd : aoSdCmd; |
signal iData : aiSdData; |
signal oData : aoSdData; |
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signal iWbCtrl : aWbSlaveCtrlInput; |
signal oWbCtrl : aWbSlaveCtrlOutput; |
signal iWbDat : aSdWbSlaveDataInput; |
signal oWbDat : aSdWbSlaveDataOutput; |
signal SdWbSlaveToWriteFifo : aoWriteFifo; |
signal WriteFifoToSdWbSlave : aiWriteFifo; |
signal iReadFifo : aiReadFifo; |
signal oReadFifo : aoReadFifo; |
signal ReadFifoQTemp : std_logic_vector(31 downto 0); |
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begin |
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135,7 → 137,11
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-- To sd controller |
iController => oSdWbSync, |
oController => iSdWbSync |
oController => iSdWbSync, |
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-- To write fifo |
oWriteFifo => SdWbSlaveToWriteFifo, |
iWriteFifo => WriteFifoToSdWbSlave |
); |
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SdController_inst: entity work.SdController(Rtl) |
179,7 → 185,9
iSdDataFromRam => SdDataFromRam, |
oSdDataToRam => SdDataToRam, |
iData => iData, |
oData => oData |
oData => oData, |
oReadFifo => oReadFifo, |
iReadFifo => iReadFifo |
); |
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DataRam_inst: entity work.SimpleDualPortedRam |
221,5 → 229,19
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); |
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WriteDataFifo_inst: entity work.WriteDataFifo |
port map ( |
data => std_logic_vector(SdWbSlaveToWriteFifo.data), |
rdclk => iSdClk, |
rdreq => oReadFifo.rdreq, |
wrclk => iWbClk, |
wrreq => SdWbSlaveToWriteFifo.wrreq, |
q => ReadFifoQTemp, |
rdempty => iReadFifo.rdempty, |
wrfull => WriteFifoToSdWbSlave.wrfull |
); |
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iReadFifo.q <= std_ulogic_vector(ReadFifoQTemp); |
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end architecture Rtl; |
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