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URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /sdhc-sc-core/trunk/src/grpSd/unitSdTop
    from Rev 124 to Rev 126
    ↔ Reverse comparison
  •

Rev 124 → Rev 126

/src/SdTop-Rtl-ea.vhdl
15,7 → 15,7
 
entity SdTop is
generic (
gUseSameClocks : boolean := true;
gUseSameClocks : boolean := false;
gClkFrequency : natural := 100E6;
gHighSpeedMode : boolean := true
);
77,10 → 77,15
signal iWbDat : aSdWbSlaveDataInput;
signal oWbDat : aSdWbSlaveDataOutput;
signal SdWbSlaveToWriteFifo : aoWriteFifo;
signal SdWbSlaveToReadFifo : aoReadFifo;
signal WriteFifoToSdWbSlave : aiWriteFifo;
signal iReadFifo : aiReadFifo;
signal oReadFifo : aoReadFifo;
signal SdWbSlaveFromReadFifo : aiReadFifo;
signal iReadWriteFifo : aiReadFifo;
signal oReadWriteFifo : aoReadFifo;
signal iWriteReadFifo : aiWriteFifo;
signal oWriteReadFifo : aoWriteFifo;
signal ReadFifoQTemp : std_logic_vector(31 downto 0);
signal WriteFifoQTemp : std_logic_vector(31 downto 0);
signal DisableSdClk : std_ulogic;
 
begin
142,7 → 147,11
 
-- To write fifo
oWriteFifo => SdWbSlaveToWriteFifo,
iWriteFifo => WriteFifoToSdWbSlave
iWriteFifo => WriteFifoToSdWbSlave,
 
-- To read fifo
oReadFifo => SdWbSlaveToReadFifo,
iReadFifo => SdWbSlaveFromReadFifo
);
 
SdController_inst: entity work.SdController(Rtl)
158,8 → 167,6
oSdCmd => SdCmdFromController,
iSdData => SdDataToController,
oSdData => SdDataFromController,
iDataRam => SdControllerFromDataRam,
oDataRam => SdControllerToDataRam,
oSdWbSlave => iSdControllerSync,
iSdWbSlave => oSdControllerSync,
oLedBank => oLedBank
183,30 → 190,15
iStrobe => SdStrobe,
iSdDataFromController => SdDataFromController,
oSdDataToController => SdDataToController,
iSdDataFromRam => SdDataFromRam,
oSdDataToRam => SdDataToRam,
iData => iData,
oData => oData,
oReadFifo => oReadFifo,
iReadFifo => iReadFifo,
oReadWriteFifo => oReadWriteFifo,
iReadWriteFifo => iReadWriteFifo,
oWriteReadFifo => oWriteReadFifo,
iWriteReadFifo => iWriteReadFifo,
oDisableSdClk => DisableSdClk
);
 
DataRam_inst: entity work.SimpleDualPortedRam
generic map (
gDataWidth => 32,
gAddrWidth => 7
)
port map (
iClk => iSdClk,
iAddrRW => SdDataToRam.Addr,
iDataRW => SdDataToRam.Data,
iWeRW => SdDataToRam.We,
oDataRW => SdDataFromRam.Data,
iAddrR => SdControllerToDataRam.Addr,
oDataR => SdControllerFromDataRam.Data
);
 
SdClockMaster_inst: entity work.SdClockMaster
generic map (
gClkFrequency => gClkFrequency
236,15 → 228,29
port map (
data => std_logic_vector(SdWbSlaveToWriteFifo.data),
rdclk => iSdClk,
rdreq => oReadFifo.rdreq,
rdreq => oReadWriteFifo.rdreq,
wrclk => iWbClk,
wrreq => SdWbSlaveToWriteFifo.wrreq,
q => ReadFifoQTemp,
rdempty => iReadFifo.rdempty,
rdempty => iReadWriteFifo.rdempty,
wrfull => WriteFifoToSdWbSlave.wrfull
);
 
iReadFifo.q <= std_ulogic_vector(ReadFifoQTemp);
iReadWriteFifo.q <= std_ulogic_vector(ReadFifoQTemp);
 
ReadDataFifo_inst: entity work.WriteDataFifo
port map (
data => std_logic_vector(oWriteReadFifo.data),
rdclk => iWbClk,
rdreq => SdWbSlaveToReadFifo.rdreq,
wrclk => iSdClk,
wrreq => oWriteReadFifo.wrreq,
q => WriteFifoQTemp,
rdempty => SdWbSlaveFromReadFifo.rdempty,
wrfull => iWriteReadFifo.wrfull
);
 
SdWbSlaveFromReadFifo.q <= std_ulogic_vector(WriteFifoQTemp);
 
end architecture Rtl;
 
/syn/SdTopsyn.tcl
18,7 → 18,7
package require ::quartus::project
package require ::quartus::flow
 
project_new TbdSdsyn -revision TbdSdSyn -overwrite
project_new SdTopsyn -revision SdTopSyn -overwrite
 
set_global_assignment -name FAMILY "Cyclone II"
set_global_assignment -name DEVICE EP2C35F484C8

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