OpenCores
URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /sdhc-sc-core/trunk/src/grpSd/unitSdWbSlave
    from Rev 151 to Rev 153
    ↔ Reverse comparison
  •

Rev 151 → Rev 153

/src/WishboneInterface.sv File deleted
/src/WbTransaction.sv
0,0 → 1,11
 
`ifndef WBTRANSACTION_SV
`define WBTRANSACTION_SV
 
class WbTransaction;
endclass
 
typedef mailbox #(WbTransaction) WbTransMb;
 
`endif
 
/src/IWishboneBus.sv
0,0 → 1,51
//
// file: WishboneInterface.sv
// author: Copyright 2010: Rainer Kastl
//
// Description: Wishbone interface
//
 
`ifndef IWISHBONEBUS
`define IWISHBONEBUS
 
interface IWishboneBus;
 
logic ERR_I;
logic RTY_I;
logic CLK_I = 1;
logic RST_I;
logic ACK_I;
logic [`cWishboneWidth-1 : 0] DAT_I;
 
logic CYC_O;
logic [6:4] ADR_O;
logic [`cWishboneWidth-1 : 0] DAT_O;
logic [`cWishboneWidth/`cWishboneWidth-1 : 0] SEL_O;
logic STB_O;
logic [`cWishboneWidth-1 : 0] TGA_O;
logic [`cWishboneWidth-1 : 0] TGC_O;
logic TGD_O;
logic WE_O;
logic LOCK_O;
aCTI CTI_O;
logic [1 : 0] BTE_O;
 
// Masters view of the interface
clocking cbMaster @(posedge CLK_I);
input ERR_I, RTY_I, ACK_I, DAT_I;
output CYC_O, ADR_O, DAT_O, SEL_O, STB_O, TGA_O, TGC_O, TGD_O, WE_O, LOCK_O, CTI_O, RST_I;
endclocking
modport Master (
input CLK_I, clocking cbMaster
);
 
// Slaves view of the interface
modport Slave (
input CLK_I, RST_I, CYC_O, ADR_O, DAT_O, SEL_O, STB_O, TGA_O, TGC_O, TGD_O, WE_O, LOCK_O, CTI_O,
output ERR_I, RTY_I, ACK_I, DAT_I
);
 
endinterface;
 
`endif
 
/src/WishboneBFM.sv
9,16 → 9,22
`ifndef WISHBONE
`define WISHBONE
 
`include "WishboneInterface.sv";
`include "IWishboneBus.sv";
`include "WbTransaction.sv";
 
class WbBFM;
 
virtual WishboneInterface.Master Bus;
virtual IWishboneBus.Master Bus;
WbTransMb TransInMb;
WbTransMb TransOutMb;
 
function new(virtual WishboneInterface.Master Bus);
function new(virtual IWishboneBus.Master Bus);
this.Bus = Bus;
endfunction
 
function void start();
endfunction
 
task Idle();
 
@(posedge this.Bus.CLK_I)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.