URL
https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk
Subversion Repositories sdhc-sc-core
Compare Revisions
- This comparison shows the changes necessary to convert path
/sdhc-sc-core/trunk/src/grpSd/unitTbdSd/src
- from Rev 136 to Rev 150
- ↔ Reverse comparison
Rev 136 → Rev 150
/TbdSd.sv
0,0 → 1,60
// |
// file: ../../unitSdVerificationTestbench/src/SdVerificationTestbench.sv |
// author: Rainer Kastl |
// |
// SystemVerilog Testbench testing SdCmd and SdController |
// |
|
`ifndef SDVERIFICATIONTESTBENCH |
`define SDVERIFICATIONTESTBENCH |
|
`include "SdCardModel.sv"; |
|
program Test(ISdBus SdBus); |
initial begin |
SdBusTransToken token; |
SdBFM SdBfm = new(SdBus); |
SDCard card = new(SdBfm); |
assert(card.randomize()); |
|
fork |
begin // generator |
end |
|
begin // monitor |
end |
|
begin // driver for SdCardModel |
card.run(); |
end |
|
join; |
|
$display("%t : Test completed.", $time); |
end |
endprogram |
|
module Testbed(); |
logic Clk = 0; |
logic nResetAsync = 0; |
|
ISdBus CardInterface(); |
|
TbdSd top( |
Clk, |
nResetAsync, |
CardInterface.Cmd, |
CardInterface.SClk, |
CardInterface.Data); |
|
always #5 Clk <= ~Clk; |
|
initial begin |
#10 nResetAsync <= 1; |
end |
|
Test tb(CardInterface); |
|
endmodule |
|
`endif |
/TbdSd-Rtl-ea.vhdl
62,9 → 62,12
signal oRty : std_ulogic; |
|
signal ErrorLed, DoneLed : std_ulogic; |
signal LedBank : std_ulogic_vector(7 downto 0); |
|
begin |
|
oLedBank <= LedBank(7 downto 1) & DoneLed; |
|
Reg : process (iClk) is |
begin |
if (rising_edge(iClk)) then |
125,7 → 128,7
ioCmd => ioCmd, |
oSclk => oSclk, |
ioData => ioData, |
oLedBank => oLedBank |
oLedBank => LedBank |
); |
|
TestWbMaster_inst : entity work.TestWbMaster |