URL
https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk
Subversion Repositories sdhc-sc-core
Compare Revisions
- This comparison shows the changes necessary to convert path
/sdhc-sc-core/trunk/src/grpSd/unitTbdSd
- from Rev 184 to Rev 185
- ↔ Reverse comparison
Rev 184 → Rev 185
/Files.tcl
File deleted
/Pins.tcl
File deleted
/src/TbdSd.sv
File deleted
/src/TbdSd-Rtl-ea.vhdl
File deleted
/sim/TbdSd.tcl
File deleted
/sim/TbdSd-unattended.tcl
File deleted
/syn/TbdSdsyn.tcl
File deleted
syn/TbdSdsyn.tcl
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: syn/TbdSdSyn.sdc
===================================================================
--- syn/TbdSdSyn.sdc (revision 184)
+++ syn/TbdSdSyn.sdc (nonexistent)
@@ -1,109 +0,0 @@
-## Generated SDC file "TbdSdSyn.sdc"
-
-## Copyright (C) 1991-2010 Altera Corporation
-## Your use of Altera Corporation's design tools, logic functions
-## and other software and tools, and its AMPP partner logic
-## functions, and any output files from any of the foregoing
-## (including device programming or simulation files), and any
-## associated documentation or information are expressly subject
-## to the terms and conditions of the Altera Program License
-## Subscription Agreement, Altera MegaCore Function License
-## Agreement, or other applicable license agreement, including,
-## without limitation, that your use is for the sole purpose of
-## programming logic devices manufactured by Altera and sold by
-## Altera or its authorized distributors. Please refer to the
-## applicable agreement for further details.
-
-
-## VENDOR "Altera"
-## PROGRAM "Quartus II"
-## VERSION "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition"
-
-## DATE "Thu Oct 21 20:31:30 2010"
-
-##
-## DEVICE "EP2C35F484C8"
-##
-
-
-#**************************************************************
-# Time Information
-#**************************************************************
-
-set_time_format -unit ns -decimal_places 3
-
-
-
-#**************************************************************
-# Create Clock
-#**************************************************************
-
-create_clock -name {iClk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {iClk}]
-
-
-#**************************************************************
-# Create Generated Clock
-#**************************************************************
-
-
-
-#**************************************************************
-# Set Clock Latency
-#**************************************************************
-
-
-
-#**************************************************************
-# Set Clock Uncertainty
-#**************************************************************
-
-
-
-#**************************************************************
-# Set Input Delay
-#**************************************************************
-
-
-
-#**************************************************************
-# Set Output Delay
-#**************************************************************
-
-
-
-#**************************************************************
-# Set Clock Groups
-#**************************************************************
-
-
-
-#**************************************************************
-# Set False Path
-#**************************************************************
-
-set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_b09:dffpipe20|dffe21a*}]
-set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_a09:dffpipe17|dffe18a*}]
-
-
-#**************************************************************
-# Set Multicycle Path
-#**************************************************************
-
-
-
-#**************************************************************
-# Set Maximum Delay
-#**************************************************************
-
-
-
-#**************************************************************
-# Set Minimum Delay
-#**************************************************************
-
-
-
-#**************************************************************
-# Set Input Transition
-#**************************************************************
-
syn/TbdSdSyn.sdc
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: syn/Makefile
===================================================================
--- syn/Makefile (revision 184)
+++ syn/Makefile (nonexistent)
@@ -1,9 +0,0 @@
-# Makefile for synthesizing crcs
-
-include ../../../../Makefile.rules
-
-all: TbdSdsyn.syn
-
-clean:
- rm -rf db incremental_db *.rbf *.sof *.pin *.pof
-