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URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /sdhc-sc-core/trunk/src/grpSd
    from Rev 112 to Rev 113
    ↔ Reverse comparison
  •

Rev 112 → Rev 113

/unitSdData/src/SdData-Rtl-a.vhdl
13,7 → 13,7
type aRegion is (startbit, data, crc, endbit);
subtype aDataOutput is std_ulogic_vector(3 downto 0);
 
subtype aBlockCounter is unsigned(LogDualis(16)-1 downto 0);
subtype aBlockCounter is unsigned(LogDualis(128)-1 downto 0);
subtype aWordCounter is unsigned(LogDualis(4)-1 downto 0);
subtype aByteCounter is unsigned(LogDualis(8)-1 downto 0);
 
108,8 → 108,9
return (to_integer(word) * 8) + to_integer(byte);
end function CalcBitAddrInWord;
 
procedure NextCounterAndSaveToRam(constant byteend : natural; constant bytedec : natural) is
procedure NextCounterAndSaveToRamWide(constant byteend : natural; constant bytedec : natural) is
begin
 
if (R.ByteCounter = byteend) then
NextR.ByteCounter <= to_unsigned(7, aByteCounter'length);
 
136,8 → 137,42
else
NextR.ByteCounter <= R.ByteCounter - bytedec;
end if;
end procedure NextCounterAndSaveToRam;
 
end procedure NextCounterAndSaveToRamWide;
procedure NextCounterAndSaveToRamUsual(constant byteend : natural; constant bytedec : natural) is
begin
 
if (R.ByteCounter = byteend) then
NextR.ByteCounter <= to_unsigned(7, aByteCounter'length);
 
if (R.WordCounter = 3) then
NextR.WordCounter <= to_unsigned(0, aWordCounter'length);
NextR.FirstSend <= cInactivated;
 
-- save word to ram
NextR.Ram.We <= cActivated;
NextR.Ram.En <= cActivated;
 
if (R.BlockCounter = 127) then
NextR.BlockCounter <= to_unsigned(0, aBlockCounter'length);
NextR.Region <= crc;
else
NextR.BlockCounter <= R.BlockCounter + 1;
end if;
else
if (R.WordCounter = 0 and R.FirstSend = cInactivated) then
NextR.Ram.Addr <= R.Ram.Addr + 1;
end if;
 
NextR.WordCounter <= R.WordCounter + 1;
end if;
else
NextR.ByteCounter <= R.ByteCounter - bytedec;
end if;
 
end procedure NextCounterAndSaveToRamUsual;
 
variable temp : std_ulogic_vector(3 downto 0);
 
begin
155,14 → 190,15
 
elsif (R.Mode = wide and iData.Data = cSdStartBits) or
(R.Mode = standard and iData.Data(0) = cSdStartBit) then
NextR.Region <= data;
NextR.State <= receive;
NextR.Region <= data;
NextR.State <= receive;
NextR.ByteCounter <= to_unsigned(7,aByteCounter'length);
NextR.WordCounter <= to_unsigned(3,aWordCounter'length);
NextR.Ram.Addr <= iSdDataFromController.StartAddr;
NextR.FirstSend <= cActivated;
NextR.Ram.Addr <= iSdDataFromController.StartAddr;
NextR.FirstSend <= cActivated;
 
if (iSdDataFromController.DataMode = widewidth) then
NextR.WordCounter <= to_unsigned(3,aWordCounter'length);
 
if (iSdDataFromController.ExpectBits = ScrBits) then
NextR.BlockCounter <= to_unsigned(1, aBlockCounter'length);
elsif (iSdDataFromController.ExpectBits = SwitchFunctionBits) then
169,7 → 205,9
NextR.BlockCounter <= to_unsigned(15, aBlockCounter'length);
end if;
else
NextR.BlockCounter <= to_unsigned(15, aBlockCounter'length);
NextR.BlockCounter <= to_unsigned(0, aBlockCounter'length);
NextR.WordCounter <= to_unsigned(0,aWordCounter'length);
 
end if;
 
elsif (iSdDataFromController.Valid = cActivated) then
260,14 → 298,30
when data =>
case iSdDataFromController.DataMode is
when usual =>
report "usual mode is not implemented" severity error;
case R.Mode is
when standard =>
NextR.Ram.Data(CalcBitAddrInWord(R.WordCounter, R.ByteCounter)) <= iData.Data(0);
ShiftIntoCrc("000" & iData.Data(0));
NextCounterAndSaveToRamUsual(0,1);
 
when wide =>
for idx in 0 to 3 loop
NextR.Ram.Data(CalcBitAddrInWord(R.WordCounter, R.ByteCounter - idx)) <= iData.Data(3 - idx);
end loop;
 
ShiftIntoCrc(std_ulogic_vector(iData.Data));
NextCounterAndSaveToRamUsual(3,4);
 
when others =>
report "Unhandled mode" severity error;
end case;
 
when widewidth =>
case R.Mode is
when standard =>
NextR.Ram.Data(CalcBitAddrInWord(R.WordCounter, R.ByteCounter)) <= iData.Data(0);
ShiftIntoCrc("000" & iData.Data(0));
NextCounterAndSaveToRam(0, 1);
NextCounterAndSaveToRamWide(0, 1);
 
when wide =>
for idx in 0 to 3 loop
274,7 → 328,7
NextR.Ram.Data(CalcBitAddrInWord(R.WordCounter, R.ByteCounter - idx)) <= iData.Data(3 - idx);
end loop;
ShiftIntoCrc(std_ulogic_vector(iData.Data));
NextCounterAndSaveToRam(3, 4);
NextCounterAndSaveToRamWide(3, 4);
 
when others =>
report "Unhandled mode" severity error;
/unitTbdSd/src/TbdSd-Rtl-ea.vhdl
301,7 → 301,7
SDTop_inst : entity work.SdTop(Rtl)
generic map (
gClkFrequency => cClkFreq,
gHighSpeedMode => false
gHighSpeedMode => true
)
port map (
iClk => iClk,
/unitSdCardModel/src/SdData.sv
18,6 → 18,7
class SdData;
Mode_t mode;
DataMode_t datamode;
logic data[$];
 
function new(Mode_t mode, DataMode_t datamode);
this.mode = mode;
35,6 → 36,8
task automatic send(virtual ISdCmd.Card ICmd, logic data[$]);
aCrc16 crc = 0;
 
this.data = data;
 
if (mode == standard) begin
data.push_front(0); // startbit
CrcOnContainer(data);
/unitSdCardModel/src/SdCardModel.sv
227,6 → 227,19
response = new(cSdCmdSendStatus, state);
response.send(ICmd);
 
// expect Read
recv();
assert(recvcmd.id == cSdCmdReadSingleBlock);
// recvcmd.arg = address
response = new(cSdCmdReadSingleBlock, state);
response.send(ICmd);
 
data = {};
for(int i = 0; i < (512 * 8) - 1; i++)
data.push_back(1);
 
sddata.send(ICmd, data);
 
-> InitDone;
 
endtask
/unitSdCardModel/src/SdCommand.sv
20,6 → 20,7
cSdCmdSendCID = 10, // [31:16] RCA
cSdCmdStopTrans = 12,
cSdCmdSendStatus = 13, // [31:16] RCA
cSdCmdReadSingleBlock = 17,
cSdCmdNextIsACMD = 55 // [31:16] RCA
} SDCommandId;
 
/pkgSd/src/Sd-p.vhdl
266,6 → 266,8
constant cSdACMDArg : aSdCmdArg := cSdDefaultRCA & X"0000"; -- [31:16] RCA
constant cSdArgAppCmdPos : natural := 5;
 
constant cSdCmdReadSingleBlock : aSdCmdId := std_ulogic_vector(to_unsigned(17, cSdCmdIdHigh));
 
constant cSdCmdACMD41 : aSdCmdId := std_ulogic_vector(to_unsigned(41, cSdCmdIdHigh));
constant cSdCmdSendSCR : aSdCmdId := std_ulogic_vector(to_unsigned(51, cSdCmdIdHigh));
constant cSdCmdSetBusWidth : aSdCmdId := std_ulogic_vector(to_unsigned(6, cSdCmdIdHigh)); -- [31:2] stuff, [1:0] bus width
/unitSdVerificationTestbench/sim/wave.do
1,35 → 1,40
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /Testbed/top/sdtop_inst/iclk
add wave -noupdate -format Logic /Testbed/top/sdtop_inst/inresetasync
add wave -noupdate -format Logic /Testbed/top/sdtop_inst/iocmd
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/iodata
add wave -noupdate -format Logic /Testbed/top/sdtop_inst/osclk
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/iodata
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/oreceivedcontent
add wave -noupdate -format Logic /Testbed/top/sdtop_inst/oreceivedcontentvalid
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/oreceiveddata
add wave -noupdate -format Logic /Testbed/top/sdtop_inst/oreceiveddatavalid
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/oledbank
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sdcmdtocontroller
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sdcmdfromcontroller
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sddatatocontroller
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sddatafromcontroller
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sddatafromram
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sddatatoram
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sdcontrollertodataram
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sdcontrollerfromdataram
add wave -noupdate -format Logic /Testbed/top/sdtop_inst/sdstrobe
add wave -noupdate -format Logic /Testbed/top/sdtop_inst/sdstrobe25mhz
add wave -noupdate -format Logic /Testbed/top/sdtop_inst/sdstrobe50mhz
add wave -noupdate -format Logic /Testbed/top/sdtop_inst/highspeed
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/icmd
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/ocmd
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/idata
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/odata
add wave -noupdate -format Logic /Testbed/top/sdtop_inst/sclk
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/counter
add wave -noupdate -format Logic /Testbed/top/sdtop_inst/sdcontroller_inst/iclk
add wave -noupdate -format Logic /Testbed/top/sdtop_inst/sdcontroller_inst/inresetasync
add wave -noupdate -format Logic /Testbed/top/sdtop_inst/sdcontroller_inst/ohighspeed
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sdcontroller_inst/isdcmd
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sdcontroller_inst/osdcmd
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sdcontroller_inst/isddata
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sdcontroller_inst/osddata
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sdcontroller_inst/idataram
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sdcontroller_inst/odataram
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sdcontroller_inst/oledbank
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sdcontroller_inst/r
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sdcontroller_inst/nextr
add wave -noupdate -format Logic /Testbed/top/sdtop_inst/sdcontroller_inst/timeoutenable
add wave -noupdate -format Logic /Testbed/top/sdtop_inst/sdcontroller_inst/timeoutdisable
add wave -noupdate -format Logic /Testbed/top/sdtop_inst/sdcontroller_inst/timeout
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sdcontroller_inst/timeoutmax
add wave -noupdate -format Logic /Testbed/top/sdtop_inst/sddata_inst/iclk
add wave -noupdate -format Logic /Testbed/top/sdtop_inst/sddata_inst/inresetasync
add wave -noupdate -format Logic /Testbed/top/sdtop_inst/sddata_inst/istrobe
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sddata_inst/isddatafromcontroller
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sddata_inst/osddatatocontroller
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sddata_inst/isddatafromram
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sddata_inst/osddatatoram
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sddata_inst/idata
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sddata_inst/odata
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sddata_inst/crcin
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sddata_inst/crcout
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sddata_inst/crcdatain
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sddata_inst/r
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sddata_inst/nextr
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {13244864 ns} 0}
WaveRestoreCursors {{Cursor 1} {10084675 ns} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
44,4 → 49,4
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {13244389 ns} {13246454 ns}
WaveRestoreZoom {10084256 ns} {10087886 ns}
/unitSdController/src/SdController-Rtl-a.vhdl
10,7 → 10,7
 
architecture Rtl of SdController is
 
type aSdControllerState is (startup, init, config, idle, invalidCard);
type aSdControllerState is (startup, init, config, idle, invalidCard, read, write);
type aCmdRegion is (CMD0, CMD8, ACMD41, CMD2, CMD3, SelectCard, CheckBusWidth, SetBusWidth, CheckSpeed, ChangeSpeed, GetStatus);
type aRegion is (idle, send, response, waitstate, senddata, receivedata, checkbusy, waitstatedata);
 
549,9 → 549,8
end if;
 
when waitstate =>
NextRegion := idle;
NextCmdRegion := CheckSpeed;
NextState := idle;
NextRegion := send;
NextState := read;
 
when others =>
report "Unhandled region" severity error;
561,6 → 560,36
report "Unhandled CmdRegion" severity error;
end case;
 
when read =>
NextR.ToSdData.DataMode <= usual;
 
case R.Region is
when send =>
NextR.ToSdCmd.Content.id <= cSdCmdReadSingleBlock;
NextR.ToSdCmd.Content.arg <= (others => '0');
NextRegion := response;
 
when response =>
if (iSdCmd.Valid = cActivated) then
if (iSdCmd.Content.id = cSdCmdReadSingleBlock) then
NextR.CardStatus <= iSdCmd.Content.arg;
NextR.Region <= receivedata;
 
else
NextR.State <= invalidCard;
end if;
elsif (Timeout = cActivated) then
NextR.State <= invalidCard;
end if;
 
when receivedata =>
when waitstatedata =>
NextR.State <= idle;
 
when others =>
report "Unhandled region";
end case;
 
when idle =>
oLedBank(6) <= cActivated;
 

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