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URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

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  • This comparison shows the changes necessary to convert path 
    /sdhc-sc-core/trunk/src/grpSd
    from Rev 121 to Rev 122
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  •

Rev 121 → Rev 122

/unitSdCardModel/src/SdData.sv
33,7 → 33,7
data.push_back(crc[i]);
endfunction
 
task automatic send(virtual ISdCmd.Card ICmd, logic data[$]);
task automatic send(virtual ISdCard.Card ICmd, logic data[$]);
aCrc16 crc = 0;
 
this.data = data;
/unitSdCardModel/src/SdCardModel.sv
13,7 → 13,7
include "../../unitSdCardModel/src/SdData.sv";
 
class SDCard;
local virtual ISdCmd.Card ICmd;
local virtual ISdCard.Card ICard;
 
local SDCardState state;
local RCA_t rca;
24,8 → 24,8
 
local event CmdReceived, InitDone;
 
function new(virtual ISdCmd CmdInterface, event CmdReceived, event InitDone);
ICmd = CmdInterface;
function new(virtual ISdCard CardInterface, event CmdReceived, event InitDone);
ICard = CardInterface;
state = new();
this.CmdReceived = CmdReceived;
this.InitDone = InitDone;
32,7 → 32,7
this.CCS = 1;
rca = 0;
mode = standard;
ICmd.cbcard.Data <= 'z;
ICard.cbcard.Data <= 'z;
endfunction
 
task reset();
40,41 → 40,41
 
// Receive a command token and handle it
task recv();
ICmd.cbcard.Cmd <= 'z;
ICard.cbcard.Cmd <= 'z;
 
repeat(8) @ICmd.cbcard;
repeat(8) @ICard.cbcard;
 
recvcmd = new();
 
wait(ICmd.cbcard.Cmd == 0);
wait(ICard.cbcard.Cmd == 0);
// Startbit
recvcmd.startbit = ICmd.cbcard.Cmd;
recvcmd.startbit = ICard.cbcard.Cmd;
 
@ICmd.cbcard;
@ICard.cbcard;
// Transbit
recvcmd.transbit = ICmd.cbcard.Cmd;
recvcmd.transbit = ICard.cbcard.Cmd;
 
// CmdID
for (int i = 5; i >= 0; i--) begin
@ICmd.cbcard;
recvcmd.id[i] = ICmd.cbcard.Cmd;
@ICard.cbcard;
recvcmd.id[i] = ICard.cbcard.Cmd;
end
 
// Arg
for (int i = 31; i >= 0; i--) begin
@ICmd.cbcard;
recvcmd.arg[i] = ICmd.cbcard.Cmd;
@ICard.cbcard;
recvcmd.arg[i] = ICard.cbcard.Cmd;
end
 
// CRC
for (int i = 6; i >= 0; i--) begin
@ICmd.cbcard;
recvcmd.crc7[i] = ICmd.cbcard.Cmd;
@ICard.cbcard;
recvcmd.crc7[i] = ICard.cbcard.Cmd;
end
 
// Endbit
@ICmd.cbcard;
recvcmd.endbit = ICmd.cbcard.Cmd;
@ICard.cbcard;
recvcmd.endbit = ICard.cbcard.Cmd;
 
recvcmd.checkFromHost();
-> CmdReceived;
102,7 → 102,7
// respond with R7: we are SD 2.00 compatible and compatible to the
// voltage
voltageresponse = new(recvcmd.arg);
voltageresponse.send(ICmd);
voltageresponse.send(ICard);
 
recvCMD55(0);
 
114,7 → 114,7
// respond with R3
ocr = new(CCS, cSdVoltageWindow);
acmd41response = new(ocr);
acmd41response.send(ICmd);
acmd41response.send(ICard);
recvCMD55(0);
 
127,7 → 127,7
// respond with R3
ocr.setBusy(cOCRDone);
acmd41response = new(ocr);
acmd41response.send(ICmd);
acmd41response.send(ICard);
 
// expect CMD2
recv();
135,7 → 135,7
 
// respond with R2
cidresponse = new();
cidresponse.send(ICmd);
cidresponse.send(ICard);
 
// expect CMD3
recv();
143,7 → 143,7
 
// respond with R3
rcaresponse = new(rca, state);
rcaresponse.send(ICmd);
rcaresponse.send(ICard);
 
// expect CMD7
recv();
153,7 → 153,7
// respond with R1, no busy
state.ReadyForData = 1;
response = new(cSdCmdSelCard, state);
response.send(ICmd);
response.send(ICard);
 
// expect ACMD51
recvCMD55(rca);
162,9 → 162,9
 
// respond with R1
response = new(cSdCmdSendSCR, state);
response.send(ICmd);
response.send(ICard);
 
repeat(2) @ICmd.cbcard;
repeat(2) @ICard.cbcard;
 
// send dummy SCR
for (int i = 0; i < 64; i++)
174,7 → 174,7
data[63-48] = 1;
 
sddata = new(standard, widewidth);
sddata.send(ICmd, data);
sddata.send(ICard, data);
 
// expect ACMD6
recvCMD55(rca);
183,7 → 183,7
assert(recvcmd.arg == 'h00000002);
 
response = new(cSdCmdSetBusWidth, state);
response.send(ICmd);
response.send(ICard);
 
sddata.mode = wide;
 
191,7 → 191,7
recv();
assert(recvcmd.id == cSdCmdSwitchFuntion);
assert(recvcmd.arg == 'h00FFFFF1);
response.send(ICmd);
response.send(ICard);
 
// send status data structure
data = {};
201,13 → 201,13
 
data[511-400] = 1;
data[511-376] = 1;
sddata.send(ICmd, data);
sddata.send(ICard, data);
 
// expect CMD6 with set
recv();
assert(recvcmd.id == cSdCmdSwitchFuntion);
assert(recvcmd.arg == 'h80FFFFF1);
response.send(ICmd);
response.send(ICard);
 
// send status data structure
data = {};
217,7 → 217,7
 
data[511-400] = 1;
data[511-376] = 1;
sddata.send(ICmd, data);
sddata.send(ICard, data);
 
// switch to 50MHz
// expect CMD13
225,22 → 225,30
assert(recvcmd.id == cSdCmdSendStatus);
assert(recvcmd.arg == rca);
response = new(cSdCmdSendStatus, state);
response.send(ICmd);
response.send(ICard);
 
-> InitDone;
 
endtask
 
task read();
SDCommandR1 response;
logic data[$];
SdData sddata;
 
// expect Read
recv();
assert(recvcmd.id == cSdCmdReadSingleBlock);
// recvcmd.arg = address
response = new(cSdCmdReadSingleBlock, state);
response.send(ICmd);
response.send(ICard);
 
data = {};
for(int i = 0; i < (512 * 8); i++)
data.push_back(1);
 
sddata.send(ICmd, data);
sddata.send(ICard, data);
 
-> InitDone;
 
endtask
 
255,7 → 263,7
 
// respond with R1
response = new(cSdCmdNextIsACMD, state);
response.send(ICmd);
response.send(ICard);
endtask
function automatic SDCommandToken getCmd();
262,20 → 270,12
return recvcmd;
endfunction
 
 
task recvCmd(input SDCommandToken cmd, output SDCommandResponse response);
case (cmd.id)
cSdCmdGoIdleState: reset();
default: $display("SDCard: CmdId %d not implemented", cmd.id);
endcase
endtask
 
endclass
 
class NoSDCard extends SDCard;
 
function new(virtual ISdCmd CmdInterface, event CmdReceived, event InitDone);
super.new(CmdInterface, CmdReceived, InitDone);
function new(virtual ISdCard CardInterface, event CmdReceived, event InitDone);
super.new(CardInterface, CmdReceived, InitDone);
endfunction
 
task automatic init();
/unitSdCardModel/src/SdCommand.sv
97,7 → 97,7
protected logic endbit;
protected logic data[$];
 
task sendData(virtual ISdCmd.Card ICmd);
task sendData(virtual ISdCard.Card ICmd);
foreach(data[i]) begin
@ICmd.cbcard
ICmd.cbcard.Cmd <= data[i];
109,7 → 109,7
endtask
 
 
task automatic send(virtual ISdCmd.Card ICmd);
task automatic send(virtual ISdCard.Card ICmd);
aCrc7 crc = 0;
data.push_back(startbit);
164,7 → 164,7
endbit = 1;
endfunction
task automatic send(virtual ISdCmd.Card ICmd);
task automatic send(virtual ISdCard.Card ICmd);
data.push_back(startbit);
data.push_back(transbit);
for(int i = 5; i >= 0; i--)
195,7 → 195,7
endbit = 1;
endfunction
 
task automatic send(virtual ISdCmd.Card ICmd);
task automatic send(virtual ISdCard.Card ICmd);
cidreg_t cidreg;
 
// fill queue
/unitSdWbSdControllerSync/src/SdWbSdControllerSync-Rtl-ea.vhdl
0,0 → 1,125
--
-- Title: Synchronizer
-- File: SdWbSdControllerSync-Rtl-ea.vhdl
-- Author: Copyright 2010: Rainer Kastl
-- Standard: VHDL'93
--
-- Description: Synchronizes ctrl and data lines between
-- SdWbSlave and SdController
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.global.all;
use work.SdWb.all;
 
entity SdWbControllerSync is
generic (
 
-- both clocks are the same, therefore we don´t need synchronization
gUseSameClocks : boolean := false;
gSyncCount : natural := 2
 
);
port (
iRstSync : in std_ulogic;
 
-- clocked by iWbClk
iWbClk : in std_ulogic;
iSdWb : in aSdWbSlaveToSdController;
oSdWb : out aSdControllerToSdWbSlave;
 
-- clocked by iSdClk
iSdClk : in std_ulogic;
iSdController : in aSdControllerToSdWbSlave;
oSdController : out aSdWbSlaveToSdController
 
);
end entity SdWbControllerSync;
 
architecture Rtl of SdWbControllerSync is
 
signal ReqOperationSync : std_ulogic;
signal ReqOperationEdge : std_ulogic;
 
signal AckOperationSync : std_ulogic;
signal AckOperationEdge : std_ulogic;
 
begin
 
-- synchronization, when different clocks are used
Sync_gen : if gUseSameClocks = false generate
 
Sync_ToSdWb: entity work.Synchronizer
generic map (
gSyncCount => gSyncCount
)
port map (
iRstSync => iRstSync,
iToClk => iWbClk,
iSignal => iSdController.ReqOperation,
oSync => ReqOperationSync
);
 
Sync_ToSdController: entity work.Synchronizer
generic map (
gSyncCount => gSyncCount
)
port map (
iRstSync => iRstSync,
iToClk => iSdClk,
iSignal => iSdWb.AckOperation,
oSync => AckOperationSync
);
 
end generate;
 
-- no synchronization, when the same clocks are used
NoSync_gen : if gUseSameClocks = true generate
 
ReqOperationSync <= iSdController.ReqOperation;
AckOperationSync <= iSdWb.AckOperation;
 
end generate;
 
-- detect egdes: every toggle is a new request / acknowledgement
ReqEdge_inst : entity work.EdgeDetector
generic map (
gEdgeDetection => cDetectAnyEdge,
gOutputRegistered => false
)
port map (
iClk => iWbClk,
iRstSync => iRstSync,
iLine => ReqOperationSync,
iClearEdgeDetected => cInactivated,
oEdgeDetected => ReqOperationEdge
);
 
AckEdge_inst : entity work.EdgeDetector
generic map (
gEdgeDetection => cDetectAnyEdge,
gOutputRegistered => false
)
port map (
iClk => iSdClk,
iRstSync => iRstSync,
iLine => AckOperationSync,
iClearEdgeDetected => cInactivated,
oEdgeDetected => AckOperationEdge
);
 
-- outputs
 
oSdWb.ReqOperation <= ReqOperationEdge;
oSdWb.ReadData <= iSdController.ReadData;
 
oSdController.AckOperation <= AckOperationEdge;
oSdController.OperationBlock <= iSdWb.OperationBlock;
oSdController.WriteData <= iSdWb.WriteData;
 
end architecture Rtl;
 
 
/unitSdTop/src/SdTop-Rtl-ea.vhdl
56,30 → 56,30
 
architecture Rtl of SdTop is
 
signal SdCmdToController : aSdCmdToController;
signal SdCmdFromController : aSdCmdFromController;
signal SdDataToController : aSdDataToController;
signal SdDataFromController : aSdDataFromController;
signal SdDataFromRam : aSdDataFromRam;
signal SdDataToRam : aSdDataToRam;
signal SdControllerToDataRam : aSdControllerToRam;
signal SdControllerFromDataRam : aSdControllerFromRam;
signal SdWbSlaveToController : aSdWbSlaveToSdController;
signal SdWbSlaveFromController : aSdControllerToSdWbSlave;
signal SdCmdToController : aSdCmdToController;
signal SdCmdFromController : aSdCmdFromController;
signal SdDataToController : aSdDataToController;
signal SdDataFromController : aSdDataFromController;
signal SdDataFromRam : aSdDataFromRam;
signal SdDataToRam : aSdDataToRam;
signal SdControllerToDataRam : aSdControllerToRam;
signal SdControllerFromDataRam : aSdControllerFromRam;
signal iSdWbSync, oSdControllerSync : aSdWbSlaveToSdController;
signal iSdControllerSync, oSdWbSync : aSdControllerToSdWbSlave;
 
signal SdStrobe : std_ulogic;
signal HighSpeed : std_ulogic;
signal SdStrobe : std_ulogic;
signal HighSpeed : std_ulogic;
 
signal iCmd : aiSdCmd;
signal oCmd : aoSdCmd;
signal iData : aiSdData;
signal oData : aoSdData;
signal iCmd : aiSdCmd;
signal oCmd : aoSdCmd;
signal iData : aiSdData;
signal oData : aoSdData;
 
signal iWbCtrl : aWbSlaveCtrlInput;
signal oWbCtrl : aWbSlaveCtrlOutput;
signal iWbDat : aSdWbSlaveDataInput;
signal oWbDat : aSdWbSlaveDataOutput;
signal iWbCtrl : aWbSlaveCtrlInput;
signal oWbCtrl : aWbSlaveCtrlOutput;
signal iWbDat : aSdWbSlaveDataInput;
signal oWbDat : aSdWbSlaveDataOutput;
 
begin
 
ioCmd <= oCmd.Cmd when oCmd.En = cActivated else 'Z';
108,6 → 108,20
Dat => iDat
);
 
SdWbControllerSync_inst: entity work.SdWbControllerSync
generic map (
gUseSameClocks => gUseSameClocks
)
port map (
iRstSync => iRstSync,
iWbClk => iWbClk,
iSdClk => iSdClk,
iSdWb => iSdWbSync,
oSdWb => oSdWbSync,
iSdController => iSdControllerSync,
oSdController => oSdControllerSync
);
 
SdWbSlave_inst : entity work.SdWbSlave
port map (
iClk => iWbClk,
118,37 → 132,12
oWbCtrl => oWbCtrl,
iWbDat => iWbDat,
oWbDat => oWbDat,
 
-- To sd controller
iController => SdWbSlaveFromController,
oController => SdWbSlaveToController
iController => oSdWbSync,
oController => iSdWbSync
);
 
 
SdClockMaster_inst: entity work.SdClockMaster
generic map (
gClkFrequency => gClkFrequency
)
port map (
iClk => iSdClk,
iRstSync => iRstSync,
iHighSpeed => HighSpeed,
oSdStrobe => SdStrobe,
oSdCardClk => oSClk
);
 
SdCardSynchronizer_inst : entity work.SdCardSynchronizer
port map (
 
iClk => iSdClk,
iRstSync => iRstSync,
iCmd => ioCmd,
iData => ioData,
oCmdSync => iCmd.Cmd,
oDataSync => iData.Data
 
);
 
SdController_inst: entity work.SdController(Rtl)
generic map (
gClkFrequency => gClkFrequency,
164,8 → 153,8
oSdData => SdDataFromController,
iDataRam => SdControllerFromDataRam,
oDataRam => SdControllerToDataRam,
oSdWbSlave => SdWbSlaveFromController,
iSdWbSlave => SdWbSlaveToController,
oSdWbSlave => iSdControllerSync,
iSdWbSlave => oSdControllerSync,
oLedBank => oLedBank
);
 
208,5 → 197,29
oDataR => SdControllerFromDataRam.Data
);
 
SdClockMaster_inst: entity work.SdClockMaster
generic map (
gClkFrequency => gClkFrequency
)
port map (
iClk => iSdClk,
iRstSync => iRstSync,
iHighSpeed => HighSpeed,
oSdStrobe => SdStrobe,
oSdCardClk => oSClk
);
 
SdCardSynchronizer_inst : entity work.SdCardSynchronizer
port map (
 
iClk => iSdClk,
iRstSync => iRstSync,
iCmd => ioCmd,
iData => ioData,
oCmdSync => iCmd.Cmd,
oDataSync => iData.Data
 
);
 
end architecture Rtl;
 
/unitSdWbSlave/src/SdWbSlave-Rtl-a.vhdl
160,7 → 160,7
when idle =>
-- save edges on the ReqOperationEdge line which would be missed otherwise
 
if (iController.ReqOperationEdge = cActivated) then
if (iController.ReqOperation = cActivated) then
 
NxR.ReqOperation <= cActivated;
 
168,10 → 168,10
 
when newOperation =>
-- send a new operation, when the controller requested it
if (R.ReqOperation = cActivated or iController.ReqOperationEdge = cActivated) then
if (R.ReqOperation = cActivated or iController.ReqOperation = cActivated) then
 
NxR.oController.OperationBlock <= R.OperationBlock;
NxR.oController.AckOperationToggle <= not R.oController.AckOperationToggle;
NxR.oController.OperationBlock <= R.OperationBlock;
NxR.oController.AckOperation <= not R.oController.AckOperation;
 
-- go to idle state, the next request will come only after the SdController received this block
 
/unitTbdSd/Files.tcl
2,15 → 2,25
Sd Sd
Crc CRCs
Rs232 Rs232
Components Ics307Values}
Components Ics307Values
Wishbone Wishbone
Sd SdWb
}
 
set units {Crc Crc {Rtl}
Sd SdCmd {Rtl}
StrobesClocks Counter {Rtl}
Sd SdController {Rtl}
Sd SdData {Rtl}
Memory SimpleDualPortedRam {Rtl}
Memory SinglePortedRam {Rtl}
Sd SdController {Rtl}
Sd SdData {Rtl}
StrobesClocks StrobeGen {Rtl}
Sd SdWbSlave {Rtl}
Sd SdClockMaster {Rtl}
Sd SdCardSynchronizer {Rtl}
Synchronization Synchronizer {Rtl}
StrobesClocks EdgeDetector {Rtl}
Sd SdWbSdControllerSync {Rtl}
Sd SdTop {Rtl}
Rs232 Rs232Tx {Rtl}
Components Ics307Configurator {Rtl}
18,4 → 28,3
Sd TbdSd {Rtl}}
 
 
 
/unitTbdSd/src/TbdSd-Rtl-ea.vhdl
46,15 → 46,15
 
signal RstSync : std_ulogic_vector(1 downto 0);
 
signal iCyc : std_ulogic;
signal iLock : std_ulogic;
signal iStb : std_ulogic;
signal iWe : std_ulogic;
signal iCti : std_ulogic_vector(2 downto 0);
signal iBte : std_ulogic_vector(1 downto 0);
signal iSel : std_ulogic_vector(0 downto 0);
signal iAdr : std_ulogic_vector(6 downto 4);
signal iDat : std_ulogic_vector(31 downto 0);
signal iCyc : std_ulogic := '0';
signal iLock : std_ulogic := '0';
signal iStb : std_ulogic := '0';
signal iWe : std_ulogic := '0';
signal iCti : std_ulogic_vector(2 downto 0) := (others => '0');
signal iBte : std_ulogic_vector(1 downto 0) := (others => '0');
signal iSel : std_ulogic_vector(0 downto 0) := (others => '0');
signal iAdr : std_ulogic_vector(6 downto 4) := (others => '0');
signal iDat : std_ulogic_vector(31 downto 0) := (others => '0');
 
signal oDat : std_ulogic_vector(31 downto 0);
signal oAck : std_ulogic;
67,7 → 67,7
begin
if (rising_edge(iClk)) then
RstSync(0) <= inResetAsync;
RstSync(1) <= not RstSync(1);
RstSync(1) <= not RstSync(0);
end if;
end process Reg;
 
/pkgSdWb/src/SdWb-p.vhdl
23,7 → 23,7
subtype aOperation is std_ulogic_vector(31 downto 0);
 
-- different valid operation values
constant cOperationRead : aOperation := (0 => '1', others => '0');
constant cOperationRead : aOperation := X"00000001";
 
 
-- addresses for register banks in SdWbSlave
52,16 → 52,16
-- ports
type aSdWbSlaveToSdController is record
 
AckOperationToggle : std_ulogic; -- every edge signals that the OperationBlock is valid
OperationBlock : aOperationBlock;
WriteData : aData; -- data to write to the card (32 bit blocks)
AckOperation : std_ulogic; -- every edge signals that the OperationBlock is valid
OperationBlock : aOperationBlock;
WriteData : aData; -- data to write to the card (32 bit blocks)
 
end record aSdWbSlaveToSdController;
 
type aSdControllerToSdWbSlave is record
 
ReqOperationEdge : std_ulogic; -- Request a new OperationBlock
ReadData : aData;
ReqOperation : std_ulogic; -- Request a new OperationBlock
ReadData : aData;
 
end record aSdControllerToSdWbSlave;
 
81,9 → 81,13
 
-- default port values
constant cDefaultSdWbSlaveToSdController : aSdWbSlaveToSdController := (
OperationBlock => cDefaultOperationBlock,
WriteData => (others => '0'),
AckOperationToggle => '0');
OperationBlock => cDefaultOperationBlock,
WriteData => (others => '0'),
AckOperation => '0');
 
constant cDefaultSdControllerToSdWbSlave : aSdControllerToSdWbSlave := (
ReqOperation => '0',
ReadData => (others => '0'));
 
end package SdWb;
 
/unitSdVerificationTestbench/Files.tcl
19,10 → 19,10
Sd SdWbSlave {Rtl}
Sd SdClockMaster {Rtl}
Sd SdCardSynchronizer {Rtl}
Sd SdTop {Rtl}
Rs232 Rs232Tx {Rtl}
Components Ics307Configurator {Rtl}
Sd TbdSd {Rtl}}
Synchronization Synchronizer {Rtl}
StrobesClocks EdgeDetector {Rtl}
Sd SdWbSdControllerSync {Rtl}
Sd SdTop {Rtl}}
 
set svunits {Sd SdCardModel
Sd SdVerificationTestbench}
/unitSdVerificationTestbench/src/SdVerificationTestbench.sv
5,24 → 5,37
// SystemVerilog Testbench testing SdCmd and SdController
//
 
`define cWishboneWidth 32
const integer cWishboneWidth = 32;
const logic cAsserted = 1;
const logic cNegated = 0;
const logic cDontCare = 'X;
 
typedef logic [2:0] aCTI;
const aCTI ClassicCycle = "000";
 
 
include "../../unitSdCardModel/src/SdCardModel.sv";
include "../../unitSdVerificationTestbench/src/SdCmdInterface.sv";
include "../../unitSdWbSlave/src/WishboneInterface.sv";
include "../../unitSdWbSlave/src/Wishbone-BFM.sv";
 
`define cCmdCount 1000
 
const logic[3:0] cSdStandardVoltage = 'b0001; // 2.7-3.6V
 
program Test(ISdCmd ICmd);
program Test(ISdCard ICmd, WishboneInterface BusInterface);
initial begin
Wishbone Bus = new(BusInterface.Master);
SDCard card = new(ICmd, $root.Testbed.CmdReceived, $root.Testbed.InitDone);
SDCommandToken recvCmd, sendCmd;
int c = 0;
 
ICmd.Clk <= 0;
#10;
ICmd.nResetAsync <= 0;
BusInterface.RST_I <= 1;
#10;
ICmd.nResetAsync <= 1;
BusInterface.RST_I <= 0;
repeat (2) @ICmd.cb;
 
36,6 → 49,9
begin // driver for SdCardModel
card.init();
 
Bus.Write('b001, 'h00000001);
Bus.Write('b000, 'h00000001);
 
/*for (int i = 0; i < `cCmdCount; i++) begin
@$root.Testbed.CardRecv;
 
66,14 → 82,35
endprogram
 
module Testbed();
ISdCmd CmdInterface();
ISdCard CardInterface();
WishboneInterface BusInterface();
 
TbdSd top(CmdInterface.Clk, CmdInterface.nResetAsync, CmdInterface.Cmd,
CmdInterface.SClk,CmdInterface.Data);
SdTop top(
BusInterface.CLK_I,
BusInterface.RST_I,
BusInterface.CYC_O,
BusInterface.LOCK_O,
BusInterface.STB_O,
BusInterface.WE_O,
BusInterface.CTI_O,
BusInterface.BTE_O,
BusInterface.SEL_O,
BusInterface.ADR_O,
BusInterface.DAT_O,
BusInterface.DAT_I,
BusInterface.ACK_I,
BusInterface.ERR_I,
BusInterface.RTY_I,
CardInterface.Clk,
CardInterface.nResetAsync,
CardInterface.Cmd,
CardInterface.SClk,
CardInterface.Data);
 
always #5 CmdInterface.Clk <= ~CmdInterface.Clk;
always #5 CardInterface.Clk <= ~CardInterface.Clk;
always #5 BusInterface.CLK_I <= ~BusInterface.CLK_I;
 
Test tb(CmdInterface);
Test tb(CardInterface, BusInterface);
 
event ApplyCommand, CardRecv, CmdReceived, GenCmd, InitDone;
 
/unitSdVerificationTestbench/src/SdCmdInterface.sv
5,8 → 5,8
// Interface for the SdCmd entity
//
 
interface ISdCmd;
logic Clk;
interface ISdCard;
logic Clk = 0;
logic nResetAsync;
wire Cmd;
logic SClk;
/unitSdVerificationTestbench/sim/wave.do
1,40 → 1,49
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -format Logic /Testbed/top/sdtop_inst/iocmd
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/iodata
add wave -noupdate -format Logic /Testbed/top/sdtop_inst/osclk
add wave -noupdate -format Logic /Testbed/top/sdtop_inst/sdcontroller_inst/iclk
add wave -noupdate -format Logic /Testbed/top/sdtop_inst/sdcontroller_inst/inresetasync
add wave -noupdate -format Logic /Testbed/top/sdtop_inst/sdcontroller_inst/ohighspeed
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sdcontroller_inst/isdcmd
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sdcontroller_inst/osdcmd
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sdcontroller_inst/isddata
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sdcontroller_inst/osddata
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sdcontroller_inst/idataram
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sdcontroller_inst/odataram
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sdcontroller_inst/oledbank
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sdcontroller_inst/r
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sdcontroller_inst/nextr
add wave -noupdate -format Logic /Testbed/top/sdtop_inst/sdcontroller_inst/timeoutenable
add wave -noupdate -format Logic /Testbed/top/sdtop_inst/sdcontroller_inst/timeoutdisable
add wave -noupdate -format Logic /Testbed/top/sdtop_inst/sdcontroller_inst/timeout
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sdcontroller_inst/timeoutmax
add wave -noupdate -format Logic /Testbed/top/sdtop_inst/sddata_inst/iclk
add wave -noupdate -format Logic /Testbed/top/sdtop_inst/sddata_inst/inresetasync
add wave -noupdate -format Logic /Testbed/top/sdtop_inst/sddata_inst/istrobe
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sddata_inst/isddatafromcontroller
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sddata_inst/osddatatocontroller
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sddata_inst/isddatafromram
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sddata_inst/osddatatoram
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sddata_inst/idata
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sddata_inst/odata
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sddata_inst/crcin
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sddata_inst/crcout
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sddata_inst/crcdatain
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sddata_inst/r
add wave -noupdate -format Literal /Testbed/top/sdtop_inst/sddata_inst/nextr
add wave -noupdate -format Event /Testbed/CmdReceived
add wave -noupdate -format Event /Testbed/InitDone
add wave -noupdate -divider CardInterface
add wave -noupdate -format Logic /Testbed/CardInterface/Clk
add wave -noupdate -format Logic /Testbed/CardInterface/nResetAsync
add wave -noupdate -format Logic /Testbed/CardInterface/Cmd
add wave -noupdate -format Logic /Testbed/CardInterface/SClk
add wave -noupdate -format Literal -radix hexadecimal /Testbed/CardInterface/Data
add wave -noupdate -divider Wishbone
add wave -noupdate -format Logic /Testbed/BusInterface/ERR_I
add wave -noupdate -format Logic /Testbed/BusInterface/RTY_I
add wave -noupdate -format Logic /Testbed/BusInterface/CLK_I
add wave -noupdate -format Logic /Testbed/BusInterface/RST_I
add wave -noupdate -format Logic /Testbed/BusInterface/ACK_I
add wave -noupdate -format Literal /Testbed/BusInterface/DAT_I
add wave -noupdate -format Logic /Testbed/BusInterface/CYC_O
add wave -noupdate -format Literal /Testbed/BusInterface/ADR_O
add wave -noupdate -format Literal /Testbed/BusInterface/DAT_O
add wave -noupdate -format Logic /Testbed/BusInterface/SEL_O
add wave -noupdate -format Logic /Testbed/BusInterface/STB_O
add wave -noupdate -format Literal /Testbed/BusInterface/TGA_O
add wave -noupdate -format Literal /Testbed/BusInterface/TGC_O
add wave -noupdate -format Logic /Testbed/BusInterface/TGD_O
add wave -noupdate -format Logic /Testbed/BusInterface/WE_O
add wave -noupdate -format Logic /Testbed/BusInterface/LOCK_O
add wave -noupdate -format Literal /Testbed/BusInterface/CTI_O
add wave -noupdate -format Literal /Testbed/BusInterface/BTE_O
add wave -noupdate -divider Controller
add wave -noupdate -format Logic /Testbed/top/sdcontroller_inst/iclk
add wave -noupdate -format Logic /Testbed/top/sdcontroller_inst/inresetasync
add wave -noupdate -format Logic /Testbed/top/sdcontroller_inst/ohighspeed
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/isdcmd
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/osdcmd
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/isddata
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/osddata
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/idataram
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/odataram
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/isdwbslave
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/osdwbslave
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/oledbank
add wave -noupdate -format Literal -expand /Testbed/top/sdcontroller_inst/r
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/nextr
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {10084675 ns} 0}
WaveRestoreCursors {{Cursor 1} {10082779 ns} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
49,4 → 58,4
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {10084256 ns} {10087886 ns}
WaveRestoreZoom {10082634 ns} {10083617 ns}
/unitSdVerificationTestbench/sim/modelsim.ini
185,27 → 185,6
; Turn off reset state transitions in FSM.
; FsmResetTrans = 0
 
NoDebug = 0
CheckSynthesis = 0
NoVitalCheck = 0
Optimize_1164 = 1
NoVital = 0
Quiet = 0
Show_source = 0
DisableOpt = 0
ZeroIn = 0
CoverageNoSub = 0
NoCoverage = 1
CoverCells = 0
CoverExcludeDefault = 0
CoverageFEC = 1
CoverageShortCircuit = 0
CoverOpt = 3
Show_Warning1 = 1
Show_Warning2 = 1
Show_Warning3 = 1
Show_Warning4 = 1
Show_Warning5 = 1
[vlog]
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
430,22 → 409,6
; Default is true (1).
; PrintSVPackageLoadingAttribute = 1
 
vlog95compat = 0
Vlog01Compat = 0
Svlog = 0
CoverCells = 0
CoverExcludeDefault = 0
CoverageFEC = 0
CoverageShortCircuit = 0
CoverOpt = 3
Quiet = 0
Show_source = 0
Protect = 0
NoDebug = 0
Hazard = 0
UpCase = 0
DisableOpt = 0
ZeroIn = 0
[sccom]
; Enable use of SCV include files and library. Default is off.
; UseScv = 1
466,10 → 429,6
; Enable use of SC_MS include files and library. Default is off.
; UseScMs = 1
 
UseScv = 0
UseScMs = 0
CppOptions =
SccomVerbose = 0
[vopt]
; Turn on code coverage in vopt. Default is off.
; Coverage = sbceft
572,7 → 531,7
 
; Stop the simulator after a VHDL/Verilog immediate assertion message
; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
BreakOnAssertion = 2
BreakOnAssertion = 3
 
; VHDL assertion Message Format
; %S - Severity Level
/unitSdController/src/SdController-Rtl-a.vhdl
10,7 → 10,7
 
architecture Rtl of SdController is
 
type aSdControllerState is (startup, init, config, idle, invalidCard, read, write);
type aSdControllerState is (startup, init, config, requestnewoperation, idle, invalidCard, read, write);
type aCmdRegion is (CMD0, CMD8, ACMD41, CMD2, CMD3, SelectCard, CheckBusWidth, SetBusWidth, CheckSpeed, ChangeSpeed, GetStatus);
type aRegion is (idle, send, response, waitstate, senddata, receivedata, checkbusy, waitstatedata);
 
24,37 → 24,41
CheckCrc => cActivated);
 
type aSdControllerReg is record
State : aSdControllerState;
CmdRegion : aCmdRegion;
Region : aRegion;
Counter : aCounter;
SendCMD55 : std_ulogic;
SentCMD55 : std_ulogic;
HCS : std_ulogic;
CCS : std_ulogic;
RCA : aSdRCA;
CardStatus : aSdCardStatus;
ToSdCmd : aSdCmdFromController;
ToSdData : aSdDataFromController;
ToDataRam : aSdControllerToRam;
HighSpeed : std_ulogic;
State : aSdControllerState;
CmdRegion : aCmdRegion;
Region : aRegion;
Counter : aCounter;
SendCMD55 : std_ulogic;
SentCMD55 : std_ulogic;
HCS : std_ulogic;
CCS : std_ulogic;
RCA : aSdRCA;
CardStatus : aSdCardStatus;
ToSdCmd : aSdCmdFromController;
ToSdData : aSdDataFromController;
ToDataRam : aSdControllerToRam;
ToSdWbSlave : aSdControllerToSdWbSlave;
HighSpeed : std_ulogic;
OperationBlock : aOperationBlock;
end record aSdControllerReg;
 
constant cDefaultSdControllerReg : aSdControllerReg := (
State => startup,
CmdRegion => CMD0,
Region => idle,
Counter => 0,
SendCMD55 => cInactivated,
SentCMD55 => cInactivated,
HCS => cActivated,
CCS => cInactivated,
RCA => cDefaultRCA,
CardStatus => cDefaultSdCardStatus,
ToSdCmd => cDefaultToSdCmd,
ToSdData => cDefaultSdDataFromController,
ToDataRam => cDefaultSdControllerToRam,
HighSpeed => cInactivated);
State => startup,
CmdRegion => CMD0,
Region => idle,
Counter => 0,
SendCMD55 => cInactivated,
SentCMD55 => cInactivated,
HCS => cActivated,
CCS => cInactivated,
RCA => cDefaultRCA,
CardStatus => cDefaultSdCardStatus,
ToSdCmd => cDefaultToSdCmd,
ToSdData => cDefaultSdDataFromController,
ToDataRam => cDefaultSdControllerToRam,
ToSdWbSlave => cDefaultSdControllerToSdWbSlave,
HighSpeed => cInactivated,
OperationBlock => cDefaultOperationBlock);
 
signal R, NextR : aSdControllerReg;
 
81,6 → 85,7
oSdCmd <= R.ToSdCmd;
oSdData <= R.ToSdData;
oDataRam <= R.ToDataRam;
oSdWbSlave <= R.ToSdWbSlave;
oHighSpeed <= R.HighSpeed;
 
Regs : process (iClk, inResetAsync)
116,11 → 121,11
if (iDataRam.Data(16) = cActivated) then
NextR.ToDataRam.Addr <= R.ToSdData.StartAddr + (511 - 376)/32;
else
NextState := idle;
NextState := requestnewoperation;
end if;
elsif (R.ToDataRam.Addr = R.ToSdData.StartAddr + (511 - 376)/32) then
if (iDataRam.Data(27 downto 24) /= X"1") then
NextState := idle;
NextState := requestnewoperation;
end if;
end if;
end procedure CheckSpeedResponse;
464,7 → 469,7
NextR.Region <= receivedata;
 
else
NextR.State <= idle;
NextR.State <= invalidCard;
end if;
elsif (Timeout = cActivated) then
NextR.State <= invalidCard;
549,8 → 554,8
end if;
 
when waitstate =>
NextRegion := send;
NextState := read;
NextRegion := idle;
NextState := requestnewoperation;
 
when others =>
report "Unhandled region" severity error;
583,16 → 588,44
end if;
 
when receivedata =>
-- TODO: send to interface
 
when waitstatedata =>
NextR.State <= idle;
NextR.Region <= idle;
NextR.State <= requestnewoperation;
 
when others =>
report "Unhandled region";
end case;
 
when requestnewoperation =>
 
NextR.ToSdWbSlave.ReqOperation <= not R.ToSdWbSlave.ReqOperation;
NextR.State <= idle;
 
when idle =>
oLedBank(6) <= cActivated;
 
-- wait for next operation
if (iSdWbSlave.AckOperation = cActivated) then
 
-- save operation
NextR.OperationBlock <= iSdWbSlave.OperationBlock;
-- handle operations
case iSdWbSlave.OperationBlock.Operation is
when cOperationRead =>
 
NextR.State <= read;
NextR.Region <= send;
 
when others =>
NextR.State <= requestnewoperation;
report "Unknown operation" severity error;
end case;
 
end if;
 
when invalidCard =>
oLedBank(7) <= cActivated;
 

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