URL
https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk
Subversion Repositories sdhc-sc-core
Compare Revisions
- This comparison shows the changes necessary to convert path
/sdhc-sc-core/trunk/src/grpSd
- from Rev 152 to Rev 153
- ↔ Reverse comparison
Rev 152 → Rev 153
/unitSdCardModel/src/SdBusTrans.sv
14,6 → 14,7
bit SendBusy = 0; |
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virtual function SdBusTransData packToData(); |
return {1}; |
endfunction |
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virtual function void unpackFromData(ref SdBusTransData data); |
44,4 → 45,6
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endclass; |
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typedef mailbox #(SdBusTransToken) SdBfmMb; |
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`endif |
/unitSdCardModel/src/SdBFM-impl.sv
11,7 → 11,7
ICard.cb.Data <= 'z; |
endfunction |
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function SdBFM::stop(int AfterCount); |
function void SdBFM::stop(int AfterCount); |
StopAfter = AfterCount; |
endfunction |
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/unitSdCardModel/src/SdBFM.sv
14,7 → 14,6
`include "SDCommandArg.sv" |
`include "SdBusTrans.sv" |
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typedef mailbox #(SdBusTrans) SdBfmMb; |
typedef enum { |
standard, |
wide |
30,7 → 29,7
extern function new(virtual ISdBus card); |
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extern task start(); // starts a thread for receiving and sending via mailboxes |
extern function stop(int AfterCount); // stop the thread |
extern function void stop(int AfterCount); // stop the thread |
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extern task send(input SdBusTrans token); |
extern task sendBusy(); |
/unitSdCardModel/src/RamAction.sv
0,0 → 1,11
`ifndef RAMACTION_SV |
`define RAMACTION_SV |
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class RamAction; |
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endclass |
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typedef mailbox #(RamAction) RamActionMb; |
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`endif |
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/unitSdCardModel/src/SdCardModel.sv
15,8 → 15,14
`include "SdCommand.sv"; |
`include "SdBFM.sv"; |
`include "Logger.sv"; |
`include "RamAction.sv"; |
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class SdCardModel; |
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RamActionMb RamActionOutMb; |
SdBfmMb SdTransOutMb; |
SdBfmMb SdTransInMb; |
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local SdBFM bfm; |
local SdCardModelState state; |
local RCA_t rca; |
25,6 → 31,7
local DataMode_t datamode; |
local Logger log; |
|
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local rand int datasize; // ram addresses = 2^datasize - 1; 512 byte blocks |
constraint cdatasize {datasize > 1; datasize <= 32;} |
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34,8 → 41,8
this.ram = new[2^(datasize-1)]; |
endfunction |
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function new(SdBFM bfm); |
this.bfm = bfm; |
function new(); |
//this.bfm = bfm; |
state = new(); |
this.CCS = 1; |
rca = 0; |
43,6 → 50,9
log = new(); |
endfunction |
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function void start(); |
endfunction |
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task reset(); |
endtask |
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303,8 → 313,8
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class NoSdCardModel extends SdCardModel; |
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function new(SdBFM bfm); |
super.new(bfm); |
function new(); |
super.new(); |
endfunction |
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task automatic init(); |
/unitSdCardModel/src/SdCommand.sv
85,7 → 85,7
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function new(); |
this.cid = new(); |
this.cid.randomize(); |
assert(this.cid.randomize()); |
endfunction |
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virtual function SdBusTransData packToData(); |
/unitSdWbSlave/src/WishboneInterface.sv
File deleted
/unitSdWbSlave/src/WbTransaction.sv
0,0 → 1,11
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`ifndef WBTRANSACTION_SV |
`define WBTRANSACTION_SV |
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class WbTransaction; |
endclass |
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typedef mailbox #(WbTransaction) WbTransMb; |
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`endif |
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/unitSdWbSlave/src/IWishboneBus.sv
0,0 → 1,51
// |
// file: WishboneInterface.sv |
// author: Copyright 2010: Rainer Kastl |
// |
// Description: Wishbone interface |
// |
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`ifndef IWISHBONEBUS |
`define IWISHBONEBUS |
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interface IWishboneBus; |
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logic ERR_I; |
logic RTY_I; |
logic CLK_I = 1; |
logic RST_I; |
logic ACK_I; |
logic [`cWishboneWidth-1 : 0] DAT_I; |
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logic CYC_O; |
logic [6:4] ADR_O; |
logic [`cWishboneWidth-1 : 0] DAT_O; |
logic [`cWishboneWidth/`cWishboneWidth-1 : 0] SEL_O; |
logic STB_O; |
logic [`cWishboneWidth-1 : 0] TGA_O; |
logic [`cWishboneWidth-1 : 0] TGC_O; |
logic TGD_O; |
logic WE_O; |
logic LOCK_O; |
aCTI CTI_O; |
logic [1 : 0] BTE_O; |
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// Masters view of the interface |
clocking cbMaster @(posedge CLK_I); |
input ERR_I, RTY_I, ACK_I, DAT_I; |
output CYC_O, ADR_O, DAT_O, SEL_O, STB_O, TGA_O, TGC_O, TGD_O, WE_O, LOCK_O, CTI_O, RST_I; |
endclocking |
modport Master ( |
input CLK_I, clocking cbMaster |
); |
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// Slaves view of the interface |
modport Slave ( |
input CLK_I, RST_I, CYC_O, ADR_O, DAT_O, SEL_O, STB_O, TGA_O, TGC_O, TGD_O, WE_O, LOCK_O, CTI_O, |
output ERR_I, RTY_I, ACK_I, DAT_I |
); |
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endinterface; |
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`endif |
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/unitSdWbSlave/src/WishboneBFM.sv
9,16 → 9,22
`ifndef WISHBONE |
`define WISHBONE |
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`include "WishboneInterface.sv"; |
`include "IWishboneBus.sv"; |
`include "WbTransaction.sv"; |
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class WbBFM; |
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virtual WishboneInterface.Master Bus; |
virtual IWishboneBus.Master Bus; |
WbTransMb TransInMb; |
WbTransMb TransOutMb; |
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function new(virtual WishboneInterface.Master Bus); |
function new(virtual IWishboneBus.Master Bus); |
this.Bus = Bus; |
endfunction |
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function void start(); |
endfunction |
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task Idle(); |
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@(posedge this.Bus.CLK_I) |
/unitSdVerificationTestbench/src/SdVerificationTestbench.sv
19,92 → 19,17
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`include "Harness.sv"; |
`include "SdCardModel.sv"; |
`include "SdBusInterface.sv"; |
`include "WishboneInterface.sv"; |
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`define cCmdCount 1000 |
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const logic[3:0] cSdStandardVoltage = 'b0001; // 2.7-3.6V |
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program Test(ISdCard ICmd, WishboneInterface BusInterface); |
program Test(ISdBus SdBus, IWishboneBus WbBus); |
initial begin |
SdCardModel card = new(ICmd, $root.Testbed.CmdReceived, $root.Testbed.InitDone); |
Logger log = new(); |
SdCardModel card; |
Harness harness; |
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assert(card.randomize()); |
BusInterface.RST_I <= 1; |
#10; |
BusInterface.RST_I <= 0; |
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repeat (2) @ICmd.cb; |
card = new(); |
harness = new(SdBus, WbBus); |
harness.Card = card; |
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fork |
begin // generator |
end |
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begin // monitor |
end |
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begin // driver for SdCardModel |
card.run(); |
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/*for (int i = 0; i < `cCmdCount; i++) begin |
@$root.Testbed.CardRecv; |
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$display("driver2: %0d", i); |
card.recv(); |
end*/ |
end |
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begin // driver for wishbone interface |
@$root.Testbed.InitDone; |
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Bus.Write('b100, 'h04030201); |
Bus.Write('b001, 'h00000001); |
Bus.Write('b000, 'h00000010); |
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#10000; |
Bus.Write('b100, 'h02020202); |
Bus.Write('b100, 'h03030303); |
Bus.Write('b100, 'h04040404); |
Bus.Write('b100, 'h05050505); |
Bus.Write('b100, 'h06060606); |
Bus.Write('b100, 'h07070707); |
Bus.Write('b100, 'h08080808); |
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for (int i = 0; i < 512; i++) |
Bus.Write('b100, 'h09090909); |
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Bus.Write('b000, 'h00000001); |
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for (int i = 0; i < 128; i++) begin |
Bus.Read('b011, rd); |
$display("Read: %h", rd); |
end |
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log.terminate(); |
$finish; |
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end |
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begin // checker |
@$root.Testbed.InitDone; |
/* |
for (int i = 0; i < `cCmdCount; i++) begin |
@$root.Testbed.CmdReceived; |
$display("checker: %0d", i); |
recvCmd = card.getCmd(); |
//recvCmd.display(); |
//sendCmd.display(); |
recvCmd.checkFromHost(); |
assert(recvCmd.equals(sendCmd) == 1); |
-> $root.Testbed.GenCmd; |
end*/ |
end |
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join; |
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$display("%t : Test completed.", $time); |
harness.start(); |
end |
endprogram |
|
112,25 → 37,25
logic Clk = 0; |
logic nResetAsync = 0; |
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ISdCard CardInterface(); |
WishboneInterface BusInterface(); |
ISdBus CardInterface(); |
IWishboneBus IWbBus(); |
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SdTop top( |
BusInterface.CLK_I, |
BusInterface.RST_I, |
BusInterface.CYC_O, |
BusInterface.LOCK_O, |
BusInterface.STB_O, |
BusInterface.WE_O, |
BusInterface.CTI_O, |
BusInterface.BTE_O, |
BusInterface.SEL_O, |
BusInterface.ADR_O, |
BusInterface.DAT_O, |
BusInterface.DAT_I, |
BusInterface.ACK_I, |
BusInterface.ERR_I, |
BusInterface.RTY_I, |
IWbBus.CLK_I, |
IWbBus.RST_I, |
IWbBus.CYC_O, |
IWbBus.LOCK_O, |
IWbBus.STB_O, |
IWbBus.WE_O, |
IWbBus.CTI_O, |
IWbBus.BTE_O, |
IWbBus.SEL_O, |
IWbBus.ADR_O, |
IWbBus.DAT_O, |
IWbBus.DAT_I, |
IWbBus.ACK_I, |
IWbBus.ERR_I, |
IWbBus.RTY_I, |
Clk, |
nResetAsync, |
CardInterface.Cmd, |
138,16 → 63,14
CardInterface.Data); |
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always #5 Clk <= ~Clk; |
always #5 BusInterface.CLK_I <= ~BusInterface.CLK_I; |
always #5 IWbBus.CLK_I <= ~IWbBus.CLK_I; |
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initial begin |
#10 nResetAsync <= 1; |
end |
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Test tb(CardInterface, BusInterface); |
Test tb(CardInterface, IWbBus); |
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event ApplyCommand, CardRecv, CmdReceived, GenCmd, InitDone; |
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endmodule |
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`endif |
/unitSdVerificationTestbench/src/Harness.sv
1,8 → 1,8
// |
// file: harness.sv |
// file: Harness.sv |
// author: Rainer Kastl |
// |
// Verification harness for SD-Core |
// Verification Harness for SD-Core |
// |
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`ifndef HARNESS_SV |
16,7 → 16,7
`include "SdCoreTransferFunction.sv"; |
`include "SdCoreChecker.sv"; |
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class harness; |
class Harness; |
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SdCoreTransactionBFM TransBfm; |
WbBFM WbBfm; |
33,12 → 33,14
Logger Log; |
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extern function new(virtual ISdBus SdBus, virtual IWishboneBus WbBus); |
extern task start(); |
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endclass |
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function harness::new(virtual ISdBus SdBus, virtual IWishboneBus WbBus); |
function Harness::new(virtual ISdBus SdBus, virtual IWishboneBus WbBus); |
Log = new(); |
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TransSeqGen = new(); |
TransBfm = new(); |
WbBfm = new(WbBus); |
SdBfm = new(SdBus); |
45,10 → 47,23
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TransFunc = new(); |
Checker = new(); |
endfunction |
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Card.randomize(); |
TransSeqGen.randomize(); |
task Harness::start(); |
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assert(Card.randomize()) else Log.error("Error randomizing card"); |
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// create Mailboxes |
TransSeqGen.TransOutMb[0] = new(1); |
TransSeqGen.TransOutMb[1] = new(1); |
TransBfm.WbTransOutMb = new(1); |
WbBfm.TransOutMb = new(1); |
TransBfm.SdTransOutMb = new(1); |
Card.RamActionOutMb = new(1); |
TransFunc.ExpectedResultOutMb = new(1); |
Card.SdTransOutMb = new(1); |
Card.SdTransInMb = new(1); |
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// connect Mailboxes |
TransFunc.TransInMb = TransSeqGen.TransOutMb[0]; |
TransBfm.SdTransInMb = TransSeqGen.TransOutMb[1]; |
57,8 → 72,19
Checker.SdTransInMb = TransBfm.SdTransOutMb; |
Checker.RamActionInMb = Card.RamActionOutMb; |
Checker.ExpectedResultInMb = TransFunc.ExpectedResultOutMb; |
SdBfm.SendTransMb = Card.SdTransOutMb; |
SdBfm.ReceivedTransMb = Card.SdTransInMb; |
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// start threads |
TransSeqGen.start(); |
TransBfm.start(); |
WbBfm.start(); |
SdBfm.start(); |
TransFunc.start(); |
Card.start(); |
Checker.start(); |
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endfunction |
endtask |
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`endif |
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/unitSdVerificationTestbench/sim/wave.do
1,90 → 1,6
onerror {resume} |
quietly WaveActivateNextPane {} 0 |
add wave -noupdate -format Logic /Testbed/BusInterface/ERR_I |
add wave -noupdate -format Logic /Testbed/BusInterface/RTY_I |
add wave -noupdate -format Logic /Testbed/BusInterface/CLK_I |
add wave -noupdate -format Logic /Testbed/BusInterface/RST_I |
add wave -noupdate -format Logic /Testbed/BusInterface/ACK_I |
add wave -noupdate -format Literal /Testbed/BusInterface/DAT_I |
add wave -noupdate -format Logic /Testbed/BusInterface/CYC_O |
add wave -noupdate -format Literal /Testbed/BusInterface/ADR_O |
add wave -noupdate -format Literal /Testbed/BusInterface/DAT_O |
add wave -noupdate -format Logic /Testbed/BusInterface/SEL_O |
add wave -noupdate -format Logic /Testbed/BusInterface/STB_O |
add wave -noupdate -format Literal /Testbed/BusInterface/TGA_O |
add wave -noupdate -format Literal /Testbed/BusInterface/TGC_O |
add wave -noupdate -format Logic /Testbed/BusInterface/TGD_O |
add wave -noupdate -format Logic /Testbed/BusInterface/WE_O |
add wave -noupdate -format Logic /Testbed/BusInterface/LOCK_O |
add wave -noupdate -format Literal /Testbed/BusInterface/CTI_O |
add wave -noupdate -format Literal /Testbed/BusInterface/BTE_O |
add wave -noupdate -divider SdWbSlave |
add wave -noupdate -format Logic /Testbed/top/sdwbslave_inst/iclk |
add wave -noupdate -format Logic /Testbed/top/sdwbslave_inst/irstsync |
add wave -noupdate -format Literal /Testbed/top/sdwbslave_inst/iwbctrl |
add wave -noupdate -format Literal /Testbed/top/sdwbslave_inst/owbctrl |
add wave -noupdate -format Literal /Testbed/top/sdwbslave_inst/iwbdat |
add wave -noupdate -format Literal /Testbed/top/sdwbslave_inst/owbdat |
add wave -noupdate -format Literal /Testbed/top/sdwbslave_inst/icontroller |
add wave -noupdate -format Literal /Testbed/top/sdwbslave_inst/ocontroller |
add wave -noupdate -format Literal /Testbed/top/sdwbslave_inst/owritefifo |
add wave -noupdate -format Literal /Testbed/top/sdwbslave_inst/iwritefifo |
add wave -noupdate -format Literal /Testbed/top/sdwbslave_inst/oreadfifo |
add wave -noupdate -format Literal /Testbed/top/sdwbslave_inst/ireadfifo |
add wave -noupdate -format Literal /Testbed/top/sdwbslave_inst/r |
add wave -noupdate -format Literal /Testbed/top/sdwbslave_inst/nxr |
add wave -noupdate -divider topsignals |
add wave -noupdate -format Logic /Testbed/top/osclk |
add wave -noupdate -format Logic /Testbed/top/iocmd |
add wave -noupdate -format Literal /Testbed/top/iodata |
add wave -noupdate -divider sdcard |
add wave -noupdate -format Logic /Testbed/CardInterface/Cmd |
add wave -noupdate -format Logic /Testbed/CardInterface/SClk |
add wave -noupdate -format Literal -radix hexadecimal /Testbed/CardInterface/Data |
add wave -noupdate -divider clockmaster |
add wave -noupdate -format Logic /Testbed/top/sdclockmaster_inst/iclk |
add wave -noupdate -format Logic /Testbed/top/sdclockmaster_inst/irstsync |
add wave -noupdate -format Logic /Testbed/top/sdclockmaster_inst/ihighspeed |
add wave -noupdate -format Logic /Testbed/top/sdclockmaster_inst/idisable |
add wave -noupdate -format Logic /Testbed/top/sdclockmaster_inst/osdstrobe |
add wave -noupdate -format Logic /Testbed/top/sdclockmaster_inst/osdcardclk |
add wave -noupdate -divider sddata |
add wave -noupdate -format Logic /Testbed/top/sddata_inst/iclk |
add wave -noupdate -format Logic /Testbed/top/sddata_inst/inresetasync |
add wave -noupdate -format Logic /Testbed/top/sddata_inst/istrobe |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/isddatafromcontroller |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/osddatatocontroller |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/idata |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/odata |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/ireadwritefifo |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/oreadwritefifo |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/iwritereadfifo |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/owritereadfifo |
add wave -noupdate -format Logic /Testbed/top/sddata_inst/odisablesdclk |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/crcin |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/crcout |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/crcdatain |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/r |
add wave -noupdate -format Literal /Testbed/top/sddata_inst/nextr |
add wave -noupdate -divider sdcontroller |
add wave -noupdate -format Logic /Testbed/top/sdcontroller_inst/iclk |
add wave -noupdate -format Logic /Testbed/top/sdcontroller_inst/inresetasync |
add wave -noupdate -format Logic /Testbed/top/sdcontroller_inst/ohighspeed |
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/isdcmd |
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/osdcmd |
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/isddata |
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/osddata |
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/isdwbslave |
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/osdwbslave |
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/oledbank |
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/r |
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/nextr |
add wave -noupdate -format Logic /Testbed/top/sdcontroller_inst/timeoutenable |
add wave -noupdate -format Logic /Testbed/top/sdcontroller_inst/timeoutdisable |
add wave -noupdate -format Logic /Testbed/top/sdcontroller_inst/timeout |
add wave -noupdate -format Literal /Testbed/top/sdcontroller_inst/timeoutmax |
TreeUpdate [SetDefaultTree] |
WaveRestoreCursors {{Cursor 1} {1132238 ns} 0} {{Cursor 2} {10084945 ns} 0} {{Cursor 3} {10085095 ns} 0} |
WaveRestoreCursors {{Cursor 1} {2020 ns} 0} {{Cursor 2} {10084945 ns} 0} {{Cursor 3} {10085095 ns} 0} |
configure wave -namecolwidth 150 |
configure wave -valuecolwidth 100 |
configure wave -justifyvalue left |
99,4 → 15,4
configure wave -timeline 0 |
configure wave -timelineunits ns |
update |
WaveRestoreZoom {1131644 ns} {1137519 ns} |
WaveRestoreZoom {0 ns} {5875 ns} |