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URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /sdhc-sc-core/trunk/src/grpSd
    from Rev 157 to Rev 158
    ↔ Reverse comparison
  •

Rev 157 → Rev 158

/unitSdCardModel/src/SdBFM-impl.sv
182,7 → 182,7
aCrc16 crc[4];
block = new();
 
for (int j = 0; j <= 512*2; j++) begin
for (int j = 0; j < 512*2; j++) begin
@ICard.cb;
for(int i = 0; i < 4; i++) begin
block.data.push_back(ICard.cb.Data[i]);
197,7 → 197,7
end
end
 
// TODO: check crc
Log.warning("TODO: Check crc in recvWideDataBlock");
 
// end bits
@ICard.cb;
/unitSdCardModel/src/RamAction.sv
1,8 → 1,14
`ifndef RAMACTION_SV
`define RAMACTION_SV
 
`include "SdCoreTransaction.sv";
 
class RamAction;
typedef enum {Read, Write} kinds;
 
kinds Kind;
int Addr;
DataBlock Data;
endclass
 
typedef mailbox #(RamAction) RamActionMb;
/unitSdCardModel/src/SdCardModel.sv
278,12 → 278,11
 
// recv data
this.bfm.receiveDataBlock(rdblock);
$display("rddata: %p", rdblock.data);
//$display("rddata: %p", rdblock.data);
//$display("datasize: %h", datasize);
//$display("Address (token): %h", token.arg);
//$display("Address: %h", addr);
 
$display("datasize: %h", datasize);
$display("Address (token): %h", token.arg);
$display("Address: %h", addr);
 
// write into ram
for (int i = 0; i < 512; i++) begin
for (int j = 7; j >= 0; j--) begin
294,7 → 293,7
this.bfm.waitUntilReady();
this.bfm.sendBusy();
$display("Ram at write address: %h", ram[addr]);
//$display("Ram at write address: %h", ram[addr]);
 
endtask
 
/unitSdWbSlave/src/WbTransaction.sv
16,9 → 16,15
rand WbData Data;
 
function void display();
$display("Transaction: %s, %s, %b, %b", Type.name(), Kind.name(), Addr, Data);
$display(toString());
endfunction
 
function string toString();
string s;
$swrite(s, "Transaction: %s, %s, %b, %b", Type.name(), Kind.name(), Addr, Data);
return s;
endfunction
 
constraint NotImplementedYet {
Type == Classic;
};
/unitSdWbSlave/src/WishboneBFM.sv
57,6 → 57,8
Log.error(msg);
end
endcase
 
TransOutMb.put(transaction);
if (StopAfter > 0) StopAfter--;
end
endtask
113,12 → 115,7
checkResponse();
 
Data = this.Bus.cbMaster.DAT_I; // latch it before the CLOCK???
begin
string msg;
$swrite(msg, "WbBus: Reading %h", Data);
Log.note(msg);
end
 
this.Bus.cbMaster.STB_O <= cNegated;
this.Bus.cbMaster.CYC_O <= cNegated;
@(posedge this.Bus.CLK_I);
/unitSdVerificationTestbench/src/Harness.sv
21,15 → 21,10
SdCoreTransactionBFM TransBfm;
WbBFM WbBfm;
SdBFM SdBfm;
 
SdCoreTransactionSeqGen TransSeqGen;
 
SdCoreTransferFunction TransFunc;
 
SdCardModel Card;
 
SdCoreChecker Checker;
 
Logger Log;
 
extern function new(virtual ISdBus SdBus, virtual IWishboneBus WbBus);
/unitSdVerificationTestbench/sim/modelsim.ini
192,7 → 192,7
Optimize_1164 = 1
NoVital = 0
Quiet = 0
Show_source = 0
Show_source = 1
DisableOpt = 0
ZeroIn = 0
CoverageNoSub = 0

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