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URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /sdhc-sc-core/trunk/src/grpStrobesClocks/unitTimeoutGenerator
    from Rev 164 to Rev 165
    Reverse comparison

Rev 164 → Rev 165

/src/TimeoutGenerator-Rtl-a.vhdl
34,32 → 34,31
 
begin
 
Regs : process (iClk, inResetAsync)
Regs : process (iClk)
begin
if (iClk'event and iClk = cActivated) then
if (iRstSync = cActivated) then
Counter <= (others => '0');
Enabled <= cInactivated;
oTimeout <= cInactivated;
else
oTimeout <= cInactivated; -- Default
 
if (inResetAsync = cnActivated) then
Counter <= (others => '0');
Enabled <= cInactivated;
oTimeout <= cInactivated;
if (iDisable = cActivated) then
Enabled <= cInactivated;
Counter <= (others => '0');
 
elsif (iClk'event and iClk = cActivated) then
oTimeout <= cInactivated; -- Default
if (iDisable = cActivated) then
Enabled <= cInactivated;
Counter <= (others => '0');
elsif (iEnable = cActivated or Enabled = cActivated) then
Counter <= Counter + 1;
Enabled <= cActivated;
 
elsif (iEnable = cActivated or Enabled = cActivated) then
Counter <= Counter + 1;
Enabled <= cActivated;
if (Counter >= cMax) then
Counter <= to_unsigned(0, cBitWidth);
Enabled <= cInactivated;
oTimeout <= cActivated;
if (Counter >= cMax) then
Counter <= to_unsigned(0, cBitWidth);
Enabled <= cInactivated;
oTimeout <= cActivated;
end if;
end if;
end if;
 
end if;
end process Regs;
 
/src/TimeoutGenerator-e.vhdl
38,7 → 38,7
 
port (
iClk : in std_ulogic;
inResetAsync : in std_ulogic;
iRstSync : in std_ulogic;
iEnable : in std_ulogic;
iDisable : in std_ulogic;
oTimeout : out std_ulogic

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