URL
https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk
Subversion Repositories sdhc-sc-core
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- This comparison shows the changes necessary to convert path
/sdhc-sc-core/trunk/src/grpStrobesClocks
- from Rev 105 to Rev 107
- ↔ Reverse comparison
Rev 105 → Rev 107
/unitCounter/src/Counter-Rtl-a.vhdl
0,0 → 1,52
-- |
-- Title: Architecture of a generic counter |
-- File: Counter-Rtl-a.vhdl |
-- Author: Copyright 2010: Rainer Kastl |
-- Standard: VHDL'93 |
-- |
-- Description: |
-- |
|
architecture Rtl of Counter is |
|
type aReg is record |
Counter : unsigned(gBitWidth - 1 downto 0); |
Enabled : std_ulogic; |
end record aReg; |
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constant cDefaultReg : aReg := ( |
Counter => (others => '1'), |
Enabled => cInactivated); |
|
signal R : aReg := cDefaultReg; |
|
begin |
|
Regs : process (iClk, inResetAsync) |
begin |
if (inResetAsync = cnActivated) then |
R <= cDefaultReg; |
elsif (iClk'event and iClk = cActivated) then |
oStrobe <= cInactivated; |
|
if (iDisable = cActivated) then |
R.Enabled <= cInactivated; |
R.Counter <= to_unsigned(0, R.Counter'length); |
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elsif (iEnable = cActivated or R.Enabled = cActivated) then |
R.Enabled <= cActivated; |
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if (R.Counter = iMax) then |
R.Counter <= to_unsigned(0, R.Counter'length); |
oStrobe <= cActivated; |
R.Enabled <= cInactivated; |
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else |
R.Counter <= R.Counter + 1; |
end if; |
|
end if; |
end if; |
end process Regs; |
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end architecture Rtl; |
/unitCounter/src/Counter-e.vhdl
0,0 → 1,28
-- |
-- Title: Generic Counter |
-- File: Counter-e.vhdl |
-- Author: Copyright 2010: Rainer Kastl |
-- Standard: VHDL'93 |
-- |
-- Description: Counts once to iMax and generates a strobe. |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
use work.Global.all; |
|
entity Counter is |
generic ( |
gBitWidth : natural |
); |
port ( |
iClk : in std_ulogic; |
inResetAsync : in std_ulogic; |
iEnable : in std_ulogic; |
iDisable : in std_ulogic; |
iMax : in unsigned(gBitWidth - 1 downto 0); |
oStrobe : out std_ulogic |
); |
end entity Counter; |
|