OpenCores
URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /sdhc-sc-core/trunk/src/grpStrobesClocks
    from Rev 121 to Rev 122
    ↔ Reverse comparison
  •

Rev 121 → Rev 122

/unitEdgeDetector/src/EdgeDetector-Rtl-a.vhdl
22,48 → 22,56
 
 
architecture Rtl of EdgeDetector is
signal nQ, detection, Q : std_ulogic;
signal nQ, detection, Q : std_ulogic;
begin -- Rtl
 
FF1 : process (iClk, inResetAsync) is
begin -- process FF1
if inResetAsync = cnActivated then
nQ <= cnInactivated;
elsif iClk'event and iClk = cActivated then -- rising clock edge
nQ <= not iLine;
end if;
end process FF1;
FF1 : process (iClk, inResetAsync) is
begin -- process FF1
if inResetAsync = cnActivated then
nQ <= cnInactivated;
elsif iClk'event and iClk = cActivated then -- rising clock edge
if (iRstSync = cActivated) then
nQ <= cnInactivated;
else
nQ <= not iLine;
end if;
end if;
end process FF1;
 
Gen : if gOutputRegistered = true generate -- only generate 2nd FF, if
-- condition is true
FF2 : process (iClk, iClearEdgeDetected, inResetAsync) is
begin -- process FF2
if inResetAsync = cnActivated then
Q <= cInactivated;
elsif iClk'event and iClk = cActivated then -- rising clock edge
if iClearEdgeDetected = cActivated then
Q <= cInactivated;
elsif detection = cActivated then
Q <= cActivated;
end if;
end if;
end process FF2;
Gen : if gOutputRegistered = true generate -- only generate 2nd FF, if
-- condition is true
FF2 : process (iClk, iClearEdgeDetected, inResetAsync) is
begin -- process FF2
if inResetAsync = cnActivated then
Q <= cInactivated;
elsif iClk'event and iClk = cActivated then -- rising clock edge
if (iRstSync = cActivated) then
Q <= cInactivated;
else
if iClearEdgeDetected = cActivated then
Q <= cInactivated;
elsif detection = cActivated then
Q <= cActivated;
end if;
end if;
end if;
end process FF2;
 
oEdgeDetected <= Q;
end generate;
oEdgeDetected <= Q;
end generate;
 
Gen2 : if gOutputRegistered = false generate
-- else detection is Output
oEdgeDetected <= detection;
end generate;
Gen2 : if gOutputRegistered = false generate
-- else detection is Output
oEdgeDetected <= detection;
end generate;
 
Detect : process (nQ, iLine) is
begin
case gEdgeDetection is
when cDetectRisingEdge => detection <= (iLine and nQ);
when cDetectFallingEdge => detection <= (iLine nor nQ);
when cDetectAnyEdge => detection <= (iLine and nQ) or (iLine nor nQ);
when others => null;
end case;
end process Detect;
Detect : process (nQ, iLine) is
begin
case gEdgeDetection is
when cDetectRisingEdge => detection <= (iLine and nQ);
when cDetectFallingEdge => detection <= (iLine nor nQ);
when cDetectAnyEdge => detection <= (iLine and nQ) or (iLine nor nQ);
when others => null;
end case;
end process Detect;
end Rtl;
/unitEdgeDetector/src/EdgeDetector-e.vhdl
4,7 → 4,7
-------------------------------------------------------------------------------
-- $Id: EdgeDetector-e.vhd,v 1.2 2004/05/09 23:35:16 fseebach Exp $
-------------------------------------------------------------------------------
-- Author : Copyright 2004: Markus Pfaff, Friedrich Seebacher
-- Author : Copyright 2004: Markus Pfaff, Friedrich Seebacher, Copyright 2010: Rainer Kastl
-- Standard : Using VHDL'93
-- Simulation : Model Technology Modelsim
-- Synthesis : Exemplar Leonardo
30,7 → 30,8
 
port (
iClk : in std_ulogic; -- system clock
inResetAsync : in std_ulogic; -- global asynchronous reset
inResetAsync : in std_ulogic := '1'; -- global asynchronous reset
iRstSync : in std_ulogic := '0'; -- global synchronous reset
iLine : in std_ulogic; -- input signal
iClearEdgeDetected : in std_ulogic; -- clear edge detected output
oEdgeDetected : out std_ulogic); -- edge detected output

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.