URL
https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk
Subversion Repositories sdhc-sc-core
Compare Revisions
- This comparison shows the changes necessary to convert path
/sdhc-sc-core/trunk/src/grpStrobesClocks
- from Rev 122 to Rev 164
- ↔ Reverse comparison
Rev 122 → Rev 164
/unitCounter/src/Counter-Rtl-a.vhdl
1,11 → 1,28
-- |
-- Title: Architecture of a generic counter |
-- File: Counter-Rtl-a.vhdl |
-- Author: Copyright 2010: Rainer Kastl |
-- Standard: VHDL'93 |
-- SDHC-SC-Core |
-- Secure Digital High Capacity Self Configuring Core |
-- |
-- Description: |
-- |
-- (C) Copyright 2010 Rainer Kastl |
-- |
-- This file is part of SDHC-SC-Core. |
-- |
-- SDHC-SC-Core is free software: you can redistribute it and/or modify it |
-- under the terms of the GNU Lesser General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or (at |
-- your option) any later version. |
-- |
-- SDHC-SC-Core is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
-- General Public License for more details. |
-- |
-- You should have received a copy of the GNU Lesser General Public License |
-- along with SDHC-SC-Core. If not, see http://www.gnu.org/licenses/. |
-- |
-- File : Counter-Rtl-a.vhdl |
-- Owner : Rainer Kastl |
-- Description : Generic counter |
-- Links : |
-- |
|
architecture Rtl of Counter is |
|
/unitCounter/src/Counter-e.vhdl
1,11 → 1,28
-- |
-- Title: Generic Counter |
-- File: Counter-e.vhdl |
-- Author: Copyright 2010: Rainer Kastl |
-- Standard: VHDL'93 |
-- SDHC-SC-Core |
-- Secure Digital High Capacity Self Configuring Core |
-- |
-- Description: Counts once to iMax and generates a strobe. |
-- |
-- (C) Copyright 2010 Rainer Kastl |
-- |
-- This file is part of SDHC-SC-Core. |
-- |
-- SDHC-SC-Core is free software: you can redistribute it and/or modify it |
-- under the terms of the GNU Lesser General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or (at |
-- your option) any later version. |
-- |
-- SDHC-SC-Core is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
-- General Public License for more details. |
-- |
-- You should have received a copy of the GNU Lesser General Public License |
-- along with SDHC-SC-Core. If not, see http://www.gnu.org/licenses/. |
-- |
-- File : Counter-e.vhdl |
-- Owner : Rainer Kastl |
-- Description : Generic Counter |
-- Links : |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
/unitStrobeGen/src/StrobeGen-Rtl-a.vhdl
1,17 → 1,29
------------------------------------------------------------------------------- |
-- Title : Strobe Generator |
-- Project : |
------------------------------------------------------------------------------- |
-- $Id: StrobeGen-Rtl-a.vhd,v 1.1 2003/04/08 13:51:09 pfaff Exp $ |
------------------------------------------------------------------------------- |
-- Author : Copyright 2003: Markus Pfaff |
-- Standard : Using VHDL'93 |
-- Simulation : Model Technology Modelsim |
-- Synthesis : Exemplar Leonardo |
------------------------------------------------------------------------------- |
-- Description: |
-- Description for synthesis. |
------------------------------------------------------------------------------- |
-- SDHC-SC-Core |
-- Secure Digital High Capacity Self Configuring Core |
-- |
-- (C) Copyright 2010 Rainer Kastl |
-- |
-- This file is part of SDHC-SC-Core. |
-- |
-- SDHC-SC-Core is free software: you can redistribute it and/or modify it |
-- under the terms of the GNU Lesser General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or (at |
-- your option) any later version. |
-- |
-- SDHC-SC-Core is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
-- General Public License for more details. |
-- |
-- You should have received a copy of the GNU Lesser General Public License |
-- along with SDHC-SC-Core. If not, see http://www.gnu.org/licenses/. |
-- |
-- File : StrobeGen-Rtl-a.vhdl |
-- Owner : Rainer Kastl |
-- Description : |
-- Links : See EDS at FH Hagenberg |
-- |
|
architecture Rtl of StrobeGen is |
|
constant max : natural := gClkFrequency/(1 sec/ gStrobeCycleTime); |
/unitStrobeGen/src/StrobeGen-e.vhdl
1,20 → 1,29
------------------------------------------------------------------------------- |
-- Title : Strobe Generator |
-- Project : General IP |
------------------------------------------------------------------------------- |
-- $Id: StrobeGen-e.vhd,v 1.1 2003/04/08 13:51:09 pfaff Exp $ |
------------------------------------------------------------------------------- |
-- Author : Copyright 2003: Markus Pfaff |
-- Standard : Using VHDL'93 |
-- Simulation : Model Technology Modelsim |
-- Synthesis : Exemplar Leonardo |
------------------------------------------------------------------------------- |
-- Description: |
-- Generates a strobe signal that will be '1' for one clock cycle of the iClk. |
-- The strobe comes every gStrobeCycleTime. If this cycle time cannot be |
-- generated exactly it will be truncated with the accuracy of one iClk cycle. |
------------------------------------------------------------------------------- |
|
-- SDHC-SC-Core |
-- Secure Digital High Capacity Self Configuring Core |
-- |
-- (C) Copyright 2010 Rainer Kastl |
-- |
-- This file is part of SDHC-SC-Core. |
-- |
-- SDHC-SC-Core is free software: you can redistribute it and/or modify it |
-- under the terms of the GNU Lesser General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or (at |
-- your option) any later version. |
-- |
-- SDHC-SC-Core is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
-- General Public License for more details. |
-- |
-- You should have received a copy of the GNU Lesser General Public License |
-- along with SDHC-SC-Core. If not, see http://www.gnu.org/licenses/. |
-- |
-- File : StrobeGen-e.vhdl |
-- Owner : Rainer Kastl |
-- Description : |
-- Links : See EDS at FH Hagenberg |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
/unitStrobeGen/src/tbStrobeGen-Bhv-ea.vhdl
1,30 → 1,38
------------------------------------------------------------------------------- |
-- Title : Testbench for design "StrobeGen" |
-- Project : |
------------------------------------------------------------------------------- |
-- $Id: tbStrobeGen-Bhv-ea.vhd,v 1.1 2004/04/26 19:31:30 fseebach Exp $ |
------------------------------------------------------------------------------- |
-- Author : Copyright 2003: Markus Pfaff |
-- Standard : Using VHDL'93 |
-- Simulation : Model Technology Modelsim |
-- Synthesis : Exemplar Leonardo; Precision |
------------------------------------------------------------------------------- |
-- Description: |
-- |
------------------------------------------------------------------------------- |
-- SDHC-SC-Core |
-- Secure Digital High Capacity Self Configuring Core |
-- |
-- (C) Copyright 2010 Rainer Kastl |
-- |
-- This file is part of SDHC-SC-Core. |
-- |
-- SDHC-SC-Core is free software: you can redistribute it and/or modify it |
-- under the terms of the GNU Lesser General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or (at |
-- your option) any later version. |
-- |
-- SDHC-SC-Core is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
-- General Public License for more details. |
-- |
-- You should have received a copy of the GNU Lesser General Public License |
-- along with SDHC-SC-Core. If not, see http://www.gnu.org/licenses/. |
-- |
-- File : tbStrobeGen-Bhv-ea.vhdl |
-- Owner : Rainer Kastl |
-- Description : |
-- Links : See EDS at FH Hagenberg |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
|
use work.Global.all; |
|
-------------------------------------------------------------------------------- |
|
entity tbStrobeGen is |
|
end entity tbStrobeGen; |
|
-------------------------------------------------------------------------------- |
|
architecture Bhv of tbStrobeGen is |
|
-- component generics |
/unitTimeoutGenerator/Files.tcl
1,3 → 1,29
# SDHC-SC-Core |
# Secure Digital High Capacity Self Configuring Core |
# |
# (C) Copyright 2010 Rainer Kastl |
# |
# This file is part of SDHC-SC-Core. |
# |
# SDHC-SC-Core is free software: you can redistribute it and/or modify it |
# under the terms of the GNU Lesser General Public License as published by |
# the Free Software Foundation, either version 3 of the License, or (at |
# your option) any later version. |
# |
# SDHC-SC-Core is distributed in the hope that it will be useful, but |
# WITHOUT ANY WARRANTY; without even the implied warranty of |
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
# General Public License for more details. |
# |
# You should have received a copy of the GNU Lesser General Public License |
# along with SDHC-SC-Core. If not, see http://www.gnu.org/licenses/. |
# |
# File : Files.tcl |
# Owner : Rainer Kastl |
# Description : |
# Links : |
# |
|
set pkgs {Global Global} |
set units {StrobesClocks TimeoutGenerator {Rtl}} |
set tb {StrobesClocks TimeoutGenerator Bhv} |
/unitTimeoutGenerator/src/tbTimeoutGenerator-Bhv-ea.vhdl
1,11 → 1,28
-- |
-- Title: Testbench for TimeoutGenerator |
-- File: tbTimeoutGenerator-Bhv-ea.vhdl |
-- Author: Copyright 2010 : Rainer Kastl |
-- Standard: VHDL'93 |
-- SDHC-SC-Core |
-- Secure Digital High Capacity Self Configuring Core |
-- |
-- Description: |
-- |
-- (C) Copyright 2010 Rainer Kastl |
-- |
-- This file is part of SDHC-SC-Core. |
-- |
-- SDHC-SC-Core is free software: you can redistribute it and/or modify it |
-- under the terms of the GNU Lesser General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or (at |
-- your option) any later version. |
-- |
-- SDHC-SC-Core is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
-- General Public License for more details. |
-- |
-- You should have received a copy of the GNU Lesser General Public License |
-- along with SDHC-SC-Core. If not, see http://www.gnu.org/licenses/. |
-- |
-- File : tbTimeoutGenerator-Bhv-ea.vhdl |
-- Owner : Rainer Kastl |
-- Description : Testbench |
-- Links : |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
/unitTimeoutGenerator/src/TimeoutGenerator-Rtl-a.vhdl
1,11 → 1,28
-- |
-- Title: Timeout Generator |
-- File: TimeoutGenerator-Rtl-a.vhdl |
-- Author: Copyright 2010: Rainer Kastl |
-- Standard: VHDL'93 |
-- SDHC-SC-Core |
-- Secure Digital High Capacity Self Configuring Core |
-- |
-- Description: Rtl for TimeoutGenerator |
-- |
-- (C) Copyright 2010 Rainer Kastl |
-- |
-- This file is part of SDHC-SC-Core. |
-- |
-- SDHC-SC-Core is free software: you can redistribute it and/or modify it |
-- under the terms of the GNU Lesser General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or (at |
-- your option) any later version. |
-- |
-- SDHC-SC-Core is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
-- General Public License for more details. |
-- |
-- You should have received a copy of the GNU Lesser General Public License |
-- along with SDHC-SC-Core. If not, see http://www.gnu.org/licenses/. |
-- |
-- File : TimeoutGenerator-Rtl-a.vhdl |
-- Owner : Rainer Kastl |
-- Description : |
-- Links : |
-- |
|
architecture Rtl of TimeoutGenerator is |
|
/unitTimeoutGenerator/src/TimeoutGenerator-e.vhdl
1,13 → 1,28
-- |
-- Title: Timeout generator |
-- File: TimeoutGenerator-e.vhdl |
-- Author: Copyright 2010: Rainer Kastl |
-- Standard: VHDL'93 |
-- SDHC-SC-Core |
-- Secure Digital High Capacity Self Configuring Core |
-- |
-- Description: Generates a strobe on the timeout line after |
-- the specified time. Only one strobe is generated after enabling |
-- the generator. |
-- |
-- (C) Copyright 2010 Rainer Kastl |
-- |
-- This file is part of SDHC-SC-Core. |
-- |
-- SDHC-SC-Core is free software: you can redistribute it and/or modify it |
-- under the terms of the GNU Lesser General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or (at |
-- your option) any later version. |
-- |
-- SDHC-SC-Core is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
-- General Public License for more details. |
-- |
-- You should have received a copy of the GNU Lesser General Public License |
-- along with SDHC-SC-Core. If not, see http://www.gnu.org/licenses/. |
-- |
-- File : TimeoutGenerator-e.vhdl |
-- Owner : Rainer Kastl |
-- Description : Generates timeout strobes after the specified time |
-- Links : |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
/unitTimeoutGenerator/sim/tbTimeoutGenerator.tcl
1,2 → 1,28
# SDHC-SC-Core |
# Secure Digital High Capacity Self Configuring Core |
# |
# (C) Copyright 2010 Rainer Kastl |
# |
# This file is part of SDHC-SC-Core. |
# |
# SDHC-SC-Core is free software: you can redistribute it and/or modify it |
# under the terms of the GNU Lesser General Public License as published by |
# the Free Software Foundation, either version 3 of the License, or (at |
# your option) any later version. |
# |
# SDHC-SC-Core is distributed in the hope that it will be useful, but |
# WITHOUT ANY WARRANTY; without even the implied warranty of |
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
# General Public License for more details. |
# |
# You should have received a copy of the GNU Lesser General Public License |
# along with SDHC-SC-Core. If not, see http://www.gnu.org/licenses/. |
# |
# File : tbTimeoutGenerator.tcl |
# Owner : Rainer Kastl |
# Description : |
# Links : |
# |
|
source ../Files.tcl |
source ../../../sim/sim.tcl |
/unitTimeoutGenerator/sim/tbTimeoutGenerator-unattended.tcl
1,3 → 1,29
# SDHC-SC-Core |
# Secure Digital High Capacity Self Configuring Core |
# |
# (C) Copyright 2010 Rainer Kastl |
# |
# This file is part of SDHC-SC-Core. |
# |
# SDHC-SC-Core is free software: you can redistribute it and/or modify it |
# under the terms of the GNU Lesser General Public License as published by |
# the Free Software Foundation, either version 3 of the License, or (at |
# your option) any later version. |
# |
# SDHC-SC-Core is distributed in the hope that it will be useful, but |
# WITHOUT ANY WARRANTY; without even the implied warranty of |
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
# General Public License for more details. |
# |
# You should have received a copy of the GNU Lesser General Public License |
# along with SDHC-SC-Core. If not, see http://www.gnu.org/licenses/. |
# |
# File : tbTimeoutGenerator-unattended.tcl |
# Owner : Rainer Kastl |
# Description : |
# Links : |
# |
|
set script tbTimeoutGenerator.tcl |
|
do "../../../sim/unattended.tcl" |
/unitEdgeDetector/src/tbEdgeDetection-Bhv-ea.vhdl
1,23 → 1,29
------------------------------------------------------------------------------- |
-- Title : Tests |
-- Project : EdgeDetector |
------------------------------------------------------------------------------- |
-- File : tbEdgeDetection-Bhv-ea.vhd |
-- Author : Rainer Kastl <hse05015@fh-hagenberg.at> |
-- Company : FH-Hagenberg |
-- Created : 2006-12-12 |
-- Last update: 2006-12-18 |
-- Platform : |
-- Standard : VHDL'93 |
------------------------------------------------------------------------------- |
-- Description: Testing of EdgeDetector |
------------------------------------------------------------------------------- |
-- Copyright (c) 2006 FH-Hagenberg |
------------------------------------------------------------------------------- |
-- Revisions : |
-- Date Version Author Description |
-- 2006-12-12 1.0 Rainer Kastl <hse05015@fh-hagenberg.at> Created |
------------------------------------------------------------------------------- |
-- SDHC-SC-Core |
-- Secure Digital High Capacity Self Configuring Core |
-- |
-- (C) Copyright 2010 Rainer Kastl |
-- |
-- This file is part of SDHC-SC-Core. |
-- |
-- SDHC-SC-Core is free software: you can redistribute it and/or modify it |
-- under the terms of the GNU Lesser General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or (at |
-- your option) any later version. |
-- |
-- SDHC-SC-Core is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
-- General Public License for more details. |
-- |
-- You should have received a copy of the GNU Lesser General Public License |
-- along with SDHC-SC-Core. If not, see http://www.gnu.org/licenses/. |
-- |
-- File : tbEdgeDetection-Bhv-ea.vhdl |
-- Owner : Rainer Kastl |
-- Description : |
-- Links : See EDS at FH Hagenberg |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use work.Global.all; |
/unitEdgeDetector/src/EdgeDetector-Rtl-a.vhdl
1,18 → 1,28
------------------------------------------------------------------------------- |
-- Title : - |
-- Project : General IP |
------------------------------------------------------------------------------- |
-- $Id: EdgeDetector-Rtl-a.vhd,v 1.1 2004/05/09 19:32:20 fseebach Exp $ |
------------------------------------------------------------------------------- |
-- Author : Copyright 2004: Markus Pfaff, Friedrich Seebacher |
-- Standard : Using VHDL'93 |
-- Simulation : Model Technology Modelsim |
-- Synthesis : Exemplar Leonardo |
------------------------------------------------------------------------------- |
-- Description: |
-- Detects an edge on the input signal. The activation is configured by the |
-- generic parameter gEdgeDetection. |
------------------------------------------------------------------------------- |
-- SDHC-SC-Core |
-- Secure Digital High Capacity Self Configuring Core |
-- |
-- (C) Copyright 2010 Rainer Kastl |
-- |
-- This file is part of SDHC-SC-Core. |
-- |
-- SDHC-SC-Core is free software: you can redistribute it and/or modify it |
-- under the terms of the GNU Lesser General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or (at |
-- your option) any later version. |
-- |
-- SDHC-SC-Core is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
-- General Public License for more details. |
-- |
-- You should have received a copy of the GNU Lesser General Public License |
-- along with SDHC-SC-Core. If not, see http://www.gnu.org/licenses/. |
-- |
-- File : EdgeDetector-Rtl-a.vhdl |
-- Owner : Rainer Kastl |
-- Description : |
-- Links : See EDS at FH Hagenberg |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
/unitEdgeDetector/src/EdgeDetector-e.vhdl
1,19 → 1,29
------------------------------------------------------------------------------- |
-- Title : - |
-- Project : General IP |
------------------------------------------------------------------------------- |
-- $Id: EdgeDetector-e.vhd,v 1.2 2004/05/09 23:35:16 fseebach Exp $ |
------------------------------------------------------------------------------- |
-- Author : Copyright 2004: Markus Pfaff, Friedrich Seebacher, Copyright 2010: Rainer Kastl |
-- Standard : Using VHDL'93 |
-- Simulation : Model Technology Modelsim |
-- Synthesis : Exemplar Leonardo |
------------------------------------------------------------------------------- |
-- Description: |
-- Detects an edge on the input signal. The activation is configured by the |
-- generic parameter gEdgeDetection. |
------------------------------------------------------------------------------- |
|
-- SDHC-SC-Core |
-- Secure Digital High Capacity Self Configuring Core |
-- |
-- (C) Copyright 2010 Rainer Kastl |
-- |
-- This file is part of SDHC-SC-Core. |
-- |
-- SDHC-SC-Core is free software: you can redistribute it and/or modify it |
-- under the terms of the GNU Lesser General Public License as published by |
-- the Free Software Foundation, either version 3 of the License, or (at |
-- your option) any later version. |
-- |
-- SDHC-SC-Core is distributed in the hope that it will be useful, but |
-- WITHOUT ANY WARRANTY; without even the implied warranty of |
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
-- General Public License for more details. |
-- |
-- You should have received a copy of the GNU Lesser General Public License |
-- along with SDHC-SC-Core. If not, see http://www.gnu.org/licenses/. |
-- |
-- File : EdgeDetector-e.vhdl |
-- Owner : Rainer Kastl |
-- Description : |
-- Links : See EDS at FH Hagenberg |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |