URL
https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk
Subversion Repositories sdhc-sc-core
Compare Revisions
- This comparison shows the changes necessary to convert path
/sdhc-sc-core/trunk/src/grpStrobesClocks
- from Rev 79 to Rev 80
- ↔ Reverse comparison
Rev 79 → Rev 80
/unitStrobeGen/src/StrobeGen-e.vhd
File deleted
unitStrobeGen/src/StrobeGen-e.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: unitStrobeGen/src/tbStrobeGen-Bhv-ea.vhd
===================================================================
--- unitStrobeGen/src/tbStrobeGen-Bhv-ea.vhd (revision 79)
+++ unitStrobeGen/src/tbStrobeGen-Bhv-ea.vhd (nonexistent)
@@ -1,98 +0,0 @@
--------------------------------------------------------------------------------
--- Title : Testbench for design "StrobeGen"
--- Project :
--------------------------------------------------------------------------------
--- $Id: tbStrobeGen-Bhv-ea.vhd,v 1.1 2004/04/26 19:31:30 fseebach Exp $
--------------------------------------------------------------------------------
--- Author : Copyright 2003: Markus Pfaff
--- Standard : Using VHDL'93
--- Simulation : Model Technology Modelsim
--- Synthesis : Exemplar Leonardo; Precision
--------------------------------------------------------------------------------
--- Description:
---
--------------------------------------------------------------------------------
-library ieee;
-use ieee.std_logic_1164.all;
-
-use work.Global.all;
-
---------------------------------------------------------------------------------
-
-entity tbStrobeGen is
-
-end entity tbStrobeGen;
-
---------------------------------------------------------------------------------
-
-architecture Bhv of tbStrobeGen is
-
- -- component generics
- constant cClkFrequency : natural := 25E6;
- constant cInResetDuration : time := 140 ns;
- constant cStrobeCycleTime : time := 1 us;
-
-
- -- component ports
- signal Clk : std_ulogic := cInactivated;
- signal nResetAsync : std_ulogic := cnInactivated;
- signal Strobe : std_ulogic;
-
-begin -- architecture Bhv
-
- -- component instantiation
- DUT : entity work.StrobeGen
- generic map (
- gClkFrequency => cClkFrequency,
- gStrobeCycleTime => cStrobeCycleTime)
- port map (
- iClk => Clk,
- inResetAsync => nResetAsync,
- oStrobe => Strobe);
-
- Clk <= not Clk after (1 sec / cClkFrequency) / 2;
-
- nResetAsync <= cnInactivated after 0 ns,
- cnActivated after cInResetDuration,
- cnInactivated after 2*cInResetDuration;
-
-
- -- Process to measure the frequency of the strobe signal and the
- -- active strobe time.
- DetermineStrobeFreq : process
- variable vHighLevel : boolean := false;
- variable vTimestamp : time := 0 sec;
- begin
- wait until (Strobe'event);
- if Strobe = '1' then
- vHighLevel := true;
- if now > vTimestamp then
- assert false
- report "Frequency Value (Strobe) = " &
- integer'image((1 sec / (now-vTimestamp))) &
- "Hz; Period (Strobe) = " &
- time'image(now-vTimestamp)
- severity note;
- end if;
- vTimestamp := now;
- elsif vHighLevel and Strobe = '0' and
- ((now-vTimestamp)<(1 sec / cClkFrequency)) then
- assert false
- report "Strobe Active Time: " & time'image(now-vTimestamp) & "; " &
- "Clock Cycle time: " & time'image((1 sec / cClkFrequency))
- severity error;
- end if;
-
- end process DetermineStrobeFreq;
-
- -- Simulation is finished after predefined time.
- SimulationFinished : process
- begin
- wait for (10*cStrobeCycleTime);
- assert false
- report "This is not a failure: Simulation finished !!!"
- severity failure;
- end process SimulationFinished;
-
-end architecture Bhv;
-
unitStrobeGen/src/tbStrobeGen-Bhv-ea.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property
Index: unitStrobeGen/src/StrobeGen-Rtl-a.vhd
===================================================================
--- unitStrobeGen/src/StrobeGen-Rtl-a.vhd (revision 79)
+++ unitStrobeGen/src/StrobeGen-Rtl-a.vhd (nonexistent)
@@ -1,38 +0,0 @@
--------------------------------------------------------------------------------
--- Title : Strobe Generator
--- Project :
--------------------------------------------------------------------------------
--- $Id: StrobeGen-Rtl-a.vhd,v 1.1 2003/04/08 13:51:09 pfaff Exp $
--------------------------------------------------------------------------------
--- Author : Copyright 2003: Markus Pfaff
--- Standard : Using VHDL'93
--- Simulation : Model Technology Modelsim
--- Synthesis : Exemplar Leonardo
--------------------------------------------------------------------------------
--- Description:
--- Description for synthesis.
--------------------------------------------------------------------------------
-architecture Rtl of StrobeGen is
-
- constant max : natural := gClkFrequency/(1 sec/ gStrobeCycleTime);
- constant cBitWidth : natural := LogDualis(max); -- Bitwidth
- signal Counter : unsigned (cBitWidth - 1 downto 0) := (others => '0');
-
-begin -- architecture Rtl
-
- StateReg : process (iClk, inResetAsync) is
- begin -- process StateReg
- if inResetAsync = cnActivated then -- asynchronous reset (active low)
- Counter <= (others => '0');
- oStrobe <= cInactivated;
- elsif iClk'event and iClk = cActivated then -- rising clock edge
- Counter <= Counter + 1;
- if Counter < max then
- oStrobe <= cInactivated;
- else
- oStrobe <= cActivated;
- Counter <= TO_UNSIGNED(1, cBitWidth);
- end if;
- end if;
- end process StateReg;
-end architecture Rtl;
unitStrobeGen/src/StrobeGen-Rtl-a.vhd
Property changes :
Deleted: svn:executable
## -1 +0,0 ##
-*
\ No newline at end of property