URL
https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk
Subversion Repositories sdhc-sc-core
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- This comparison shows the changes necessary to convert path
/sdhc-sc-core/trunk/src/grpWishbone/unitWbSlave/src
- from Rev 23 to Rev 25
- ↔ Reverse comparison
Rev 23 → Rev 25
/WbSlave-Rtl-ea.vhdl
59,10 → 59,13
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architecture Rtl of WbSlave is |
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type aWbState is (idle); |
type aWbState is (idle, ClassicRead, ClassicWrite); |
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signal State, NextState : aWbState := idle; |
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constant cValid : std_ulogic_vector(gPortSize - 1 downto 0) := (others => |
'1'); |
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begin |
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WbStateReg : process (iClk, iRstSync) |
81,7 → 84,46
-- Default Assignments |
oDat <= (others => cInactivated); |
oWbSlave <= cDefaultWbSlaveCtrlOutput; |
NextState <= State; |
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-- Determine next state |
case State is |
when idle => |
if iWbSlave.Cyc = cActivated and iWbSlave.Stb = cActivated then |
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case iWbSlave.Cti is |
when cCtiClassicCycle => |
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if (iWbSlave.We = cInactivated) then |
NextState <= ClassicRead; |
elsif (iWbSlave.We = cActivated) then |
NextState <= ClassicWrite; |
end if; |
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when others => null; |
end case; |
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end if; |
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when ClassicRead => |
assert (iWbSlave.Cyc = cActivated) report |
"Cyc deactivated mid cyclus" severity warning; |
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oWbSlave.Ack <= cActivated; |
oDat <= cValid; -- TODO: Read real data, use Sel |
NextState <= idle; |
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when ClassicWrite => |
assert (iWbSlave.Cyc = cActivated) report |
"Cyc deactivated mid cyclus" severity warning; |
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oWbSlave.Ack <= cActivated; |
-- TODO: Save data, use Sel |
NextState <= idle; |
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when others => null; |
end case; |
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end process WbNextStateAndOutputs; |
end architecture Rtl; |
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/tbWbSlave-Bhv-ea.vhdl
0,0 → 1,54
------------------------------------------------- |
-- file: tbWbSlave-Bhv-ea.vhdl |
-- author: Rainer Kastl |
-- |
-- Testbench for wishbone slave (WbSlave-Rtl-ea.vhdl) |
------------------------------------------------- |
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library ieee; |
use ieee.std_logic_1164.all; |
--use ieee.math_real.all; |
use work.Global.all; |
use work.wishbone.all; |
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entity tbWbSlave is |
generic (gClkPeriod : time := 10 ns); |
end entity; |
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architecture Bhv of tbWbSlave is |
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signal Clk, RstSync : std_ulogic := cInactivated; |
signal iWbSlave : aWbSlaveCtrlInput; |
signal oWbSlave : aWbSlaveCtrlOutput; |
signal Sel : std_ulogic_vector(0 downto 0); |
signal Adr : std_ulogic_vector(7 downto 2); |
signal DataToSlave, DataFromSlave : std_ulogic_vector(7 downto 0); |
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begin |
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-- Clock generator |
Clk <= not Clk after gClkPeriod/2; |
RstSync <= cActivated after 2*gClkPeriod, |
cInactivated after 3*gClkPeriod; |
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Stimulus : process |
begin |
wait; |
end process Stimulus ; |
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duv : entity work.WbSlave(Rtl) |
generic map (gPortSize => 8, |
gPortGranularity => 8, |
gMaximumOperandSize => 8, |
gEndian => little) |
port map(iClk => Clk, |
iRstSync => RstSync, |
iWbSlave => iWbSlave, |
oWbSlave => oWbSlave, |
iSel => Sel, |
iAdr => Adr, |
iDat => DataToSlave, |
oDat => DataFromSlave); |
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end architecture Bhv; |
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