OpenCores
URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /sdhc-sc-core/trunk/src/grpWishbone/unitWbSlave
    from Rev 19 to Rev 20
    Reverse comparison

Rev 19 → Rev 20

/src/WbSlave-Rtl-ea.vhdl
4,6 → 4,7
--
-- Generic implementation of a wishbone slave.
-- Wishbone specification revision B.3
-- Supports synchronous cycle termination.
-------------------------------------------------
 
library ieee;
13,51 → 14,56
 
entity WbSlave is
generic (
gPortSize: natural := 8; -- in bits, only 8, 16, 32 and 64 are valid
gPortGranularity : natural := 8; --in bits, only 8, 16, 32 and 64 are valid
gMaximumOperandSize : natural := 8; -- in bits, only 8, 16, 32 and 64 are valid
gEndian : endianness := big -- if the port size equals the granularity
gPortSize : natural := 8; -- in bits, only 8, 16, 32 and 64 are valid
gPortGranularity : natural := 8; -- in bits, only 8, 16, 32 and 64 are valid
gMaximumOperandSize : natural := 8; -- in bits, only 8, 16, 32 and 64 are valid
gEndian : endianness := big -- if the port size equals the granularity
-- this setting does not make a difference
);
port (
-- Control
iClk : std_ulogic; -- Clock, rising clock edge
iRst : std_ulogic; -- Reset, active high
-- Control
iClk : in std_ulogic; -- Clock, rising clock edge
iRstSync : in std_ulogic; -- Reset, active high, synchronous
 
oAck : std_ulogic; -- Indicates the end of a normal bus cycle
oErr : std_ulogic; -- Indicates an error
oRty : std_ulogic; -- Indicates that the request should be retried
iCyc : std_ulogic; -- Indicates a bus cycle
iLock : std_ulogic; -- Indicates that the current cycle is not interruptable
iSel : std_ulogic_vector(gPortSize/gPortGranularity - 1 downto 0); -- TODO:
-- Check this
iStb : std_ulogic; -- Indicates the selection of the slave
iWe : std_ulogic; -- Write enable, indicates whether the cycle is a read or
-- write cycle
iCyc : in std_ulogic; -- Indicates a bus cycle
iLock : in std_ulogic; -- Indicates that the current cycle is not interruptable
iSel : in std_ulogic_vector(gPortSize/gPortGranularity - 1 downto 0); -- TODO Check this
iStb : in std_ulogic; -- Indicates the selection of the slave
iWe : in std_ulogic; -- Write enable, indicates whether the cycle is a read or write cycle
oAck : out std_ulogic; -- Indicates the end of a normal bus cycle
oErr : out std_ulogic; -- Indicates an error
oRty : out std_ulogic; -- Indicates that the request should be retried
 
-- Data
iAdr : std_ulogic_vector(gPortSize-1 downto integer(log2(
real(gPortGranularity) )) - 1);
iDat : std_ulogic_vector(gPortSize-1 downto 0); -- Data input
oDat : std_ulogic_vector(gPortSize-1 downto 0) -- Data output
iCti : in aCti := "000"; -- used for synchronous cycle termination
iBte : in aBte; -- Burst type extension
 
-- Tags are currently not supported
);
-- Data
iAdr : in std_ulogic_vector(gPortSize-1 downto integer(log2(
real(gPortGranularity) )) - 1); -- address
 
begin
iDat : in std_ulogic_vector(gPortSize-1 downto 0); -- Data input
oDat : out std_ulogic_vector(gPortSize-1 downto 0) -- Data output
 
assert (gPortSize = 8 or gPortSize = 16 or gPortSize = 32 or gPortSize =
64) report "gPortSize is invalid." severity failure;
-- Tags are currently not supported
);
 
assert (gPortGranularity = 8 or gPortGranularity = 16 or
gPortGranularity = 32 or gPortGranularity = 64) report "gPortGranularity is invalid." severity failure;
begin
 
assert (gMaximumOperandSize = 8 or gMaximumOperandSize = 16 or
gMaximumOperandSize = 32 or gMaximumOperandSize = 64) report
"gMaximumOperandSize is invalid." severity failure;
assert (gPortSize = 8 or gPortSize = 16 or gPortSize = 32 or gPortSize =
64) report "gPortSize is invalid." severity failure;
 
assert (gPortGranularity = 8 or gPortGranularity = 16 or
gPortGranularity = 32 or gPortGranularity = 64) report "gPortGranularity is invalid." severity failure;
 
assert (gMaximumOperandSize = 8 or gMaximumOperandSize = 16 or
gMaximumOperandSize = 32 or gMaximumOperandSize = 64) report
"gMaximumOperandSize is invalid." severity failure;
 
end entity;
 
architecture Rtl of WbSlave is
 
begin
 
end architecture Rtl;
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.