URL
https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk
Subversion Repositories sdhc-sc-core
Compare Revisions
- This comparison shows the changes necessary to convert path
/sdhc-sc-core/trunk/src/grpWishbone/unitWbSlave
- from Rev 26 to Rev 27
- ↔ Reverse comparison
Rev 26 → Rev 27
/src/WbSlave-Rtl-ea.vhdl
81,10 → 81,10
end if; |
end process WbStateReg ; |
|
WbNextStateAndOutputs : process (iWbSlave, iSel, iDat, iAdr) |
WbNextStateAndOutputs : process (iWbSlave, iSel, iDat, iAdr, State) |
begin |
-- Default Assignments |
oDat <= (others => cInactivated); |
oDat <= (others => 'X'); |
oWbSlave <= cDefaultWbSlaveCtrlOutput; |
NextState <= State; |
|
/src/tbWbSlave-Bhv-ea.vhdl
24,16 → 24,42
signal Adr : std_ulogic_vector(7 downto 2); |
signal DataToSlave, DataFromSlave : std_ulogic_vector(7 downto 0); |
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signal Finished : std_ulogic := cInactivated; |
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constant cValid : std_ulogic_vector(7 downto 0) := (others => |
'1'); |
|
begin |
|
-- Clock generator |
Clk <= not Clk after gClkPeriod/2; |
Clk <= not Clk after gClkPeriod/2 when (Finished = cInactivated); |
RstSync <= cActivated after 2*gClkPeriod, |
cInactivated after 3*gClkPeriod; |
|
Stimulus : process |
begin |
wait; |
wait for 6*gClkPeriod; |
-- Classic Reads |
wait until Clk = cActivated; |
iWbSlave.Cyc <= cActivated; |
iWbSlave.Stb <= cActivated; |
iWbSlave.We <= cInactivated; |
iWbSlave.Cti <= cCtiClassicCycle; |
Adr <= "000001"; |
Sel <= "1"; |
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wait until Clk = cActivated; |
wait until Clk = cActivated; |
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assert (oWbSlave.Ack = cActivated) report |
"Read not acknowledged. Waitstate?" severity error; |
assert (DataFromSlave = cValid) report |
"Invalid data after read" severity error; |
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wait until Clk = cActivated; |
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Finished <= cActivated; |
wait; |
end process Stimulus; |
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duv : entity work.WbSlave(Rtl) |