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URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

Compare Revisions

  • This comparison shows the changes necessary to convert path
    /sdhc-sc-core/trunk/src
    from Rev 35 to Rev 36
    Reverse comparison

Rev 35 → Rev 36

/grpSd/unitSdCmd/src/SdCmd-Rtl-ea.vhdl
59,18 → 59,11
end if;
end procedure NextStateWhenAllSent;
 
begin
-- CRC calculation needs one cycle. Therefore we have to start it
-- ahead of putting the data on ioCmd.
 
 
procedure SendBitsAndCalcCrc (signal container : in std_ulogic_vector; constant toState : in aSdCmdState) is
begin
ioCmd <= container(to_integer(NextCounter));
CrcData <= container(to_integer(NextCounter));
CrcDataIn <= cActivated;
NextStateWhenAllSent(container'length, toState);
end procedure SendBitsAndCalcCrc;
 
 
begin
-- defaults
NextState <= State;
NextCounter <= Counter;
ioCmd <= 'Z';
95,10 → 88,9
ioCmd <= cSdTransBitHost;
NextState <= cmdid;
CrcDataIn <= cActivated;
CrcData <= iCmdContent.id(to_integer(NextCounter));
CrcData <= iCmdContent.id(0);
 
when cmdid =>
-- SendBitsAndCalcCrc(iCmdContent.id, arg);
ioCmd <= iCmdContent.id(to_integer(NextCounter));
if (NextCounter < iCmdContent.id'length-2) then
CrcData <= iCmdContent.id(to_integer(NextCounter)+1);
110,7 → 102,6
 
 
when arg =>
-- SendBitsAndCalcCrc(iCmdContent.arg, crc);
ioCmd <= iCmdContent.arg(to_integer(NextCounter));
if (NextCounter < iCmdContent.arg'length-2) then
CrcData <= iCmdContent.arg(to_integer(NextCounter)+1);
/grpSd/unitSdCmd/src/tbSdCmd-Bhv-ea.vhdl
21,7 → 21,7
signal Finished : std_ulogic := cInactivated;
signal nResetAsync : std_ulogic;
signal CmdContent : aSdCmdContent;
signal Cmd : std_ulogic;
signal Cmd : std_logic;
 
signal sentCmd : std_ulogic_vector(47 downto 0) := (others => 'U');
signal counter : integer := 0;
51,7 → 51,7
end process SaveCmd ;
 
-- Stimuli:
-- Cmd <= 'L';
Cmd <= 'Z';
CmdContent.id <= cSdCmdGoIdleState;
CmdContent.arg <= (others => '0');
 
/grpSd/unitSdCmd/sim/wave.do
7,6 → 7,7
add wave -noupdate -format Logic /tbsdcmd/cmd
add wave -noupdate -format Literal /tbsdcmd/sentcmd
add wave -noupdate -format Literal /tbsdcmd/counter
add wave -noupdate -format Logic /tbsdcmd/save
add wave -noupdate -format Logic /tbsdcmd/dut/iocmd
add wave -noupdate -format Literal /tbsdcmd/dut/state
add wave -noupdate -format Literal /tbsdcmd/dut/nextstate
28,7 → 29,7
add wave -noupdate -format Literal /tbsdcmd/dut/crc7_inst/oparallel
add wave -noupdate -format Literal /tbsdcmd/dut/crc7_inst/regs
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {194 ns} 0}
WaveRestoreCursors {{Cursor 1} {35 ns} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
/grpSd/unitSdCmd/sim/modelsim.ini
185,6 → 185,27
; Turn off reset state transitions in FSM.
; FsmResetTrans = 0
 
NoDebug = 0
CheckSynthesis = 0
NoVitalCheck = 0
Optimize_1164 = 1
NoVital = 0
Quiet = 0
Show_source = 0
DisableOpt = 0
ZeroIn = 0
CoverageNoSub = 0
NoCoverage = 1
CoverCells = 0
CoverExcludeDefault = 0
CoverageFEC = 1
CoverageShortCircuit = 0
CoverOpt = 3
Show_Warning1 = 1
Show_Warning2 = 1
Show_Warning3 = 1
Show_Warning4 = 1
Show_Warning5 = 1
[vlog]
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
409,6 → 430,23
; Default is true (1).
; PrintSVPackageLoadingAttribute = 1
 
vlog95compat = 0
Vlog01Compat = 0
Svlog = 0
CoverCells = 0
CoverExcludeDefault = 0
CoverageFEC = 0
CoverageShortCircuit = 0
CoverOpt = 3
OptionFile = /home/draugdel/SD-CORE/src/grpSd/unitSdCmd/sim/vlog.opt
Quiet = 0
Show_source = 0
Protect = 0
NoDebug = 0
Hazard = 0
UpCase = 0
DisableOpt = 0
ZeroIn = 0
[sccom]
; Enable use of SCV include files and library. Default is off.
; UseScv = 1
429,6 → 467,10
; Enable use of SC_MS include files and library. Default is off.
; UseScMs = 1
 
UseScv = 0
UseScMs = 0
CppOptions =
SccomVerbose = 0
[vopt]
; Turn on code coverage in vopt. Default is off.
; Coverage = sbceft

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