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Rev 120 → Rev 121

/src/grpSd/unitTbdSd/src/TbdSd-Rtl-ea.vhdl
17,8 → 17,7
 
entity TbdSd is
generic (
gClkFreq : natural := 100E6;
gDebug : boolean := false
gClkFrequency : natural := 100E6
);
port (
iClk : std_ulogic;
45,240 → 44,37
 
architecture Rtl of TbdSd is
 
constant cClkFreq : natural := gClkFreq;
constant cBaudRate : natural := 115200;
signal RstSync : std_ulogic_vector(1 downto 0);
 
signal iRs232Tx : aiRs232Tx;
signal oRs232Tx : aoRs232Tx;
signal iCyc : std_ulogic;
signal iLock : std_ulogic;
signal iStb : std_ulogic;
signal iWe : std_ulogic;
signal iCti : std_ulogic_vector(2 downto 0);
signal iBte : std_ulogic_vector(1 downto 0);
signal iSel : std_ulogic_vector(0 downto 0);
signal iAdr : std_ulogic_vector(6 downto 4);
signal iDat : std_ulogic_vector(31 downto 0);
 
type aReadState is (waitforchange, send);
type aWriteState is (idle, id, arg, data, crc);
type aRamMode is (read, write);
signal oDat : std_ulogic_vector(31 downto 0);
signal oAck : std_ulogic;
signal oErr : std_ulogic;
signal oRty : std_ulogic;
 
type aReg is record
ReadState : aReadState;
ReadCounter : natural;
WriteState : aWriteState;
WriteCounter : natural;
RamMode : aRamMode;
Data : std_ulogic_vector(7 downto 0);
RamBuffer : std_ulogic_vector(31 downto 0);
DataAvailable : std_ulogic;
RamReadAddr : natural range 0 to 2**8-1;
RamAddr : natural range 0 to 2**8-1;
RamWriteAddr : natural range 0 to 2**8-1;
RamWe : std_ulogic;
RamData : std_ulogic_vector(31 downto 0);
end record aReg;
 
constant cDefaultReg : aReg := (
ReadState => waitforchange,
ReadCounter => 0,
WriteState => idle,
WriteCounter => 0,
RamMode => read,
Data => (others => '0'),
RamBuffer => (others => '0'),
DataAvailable => cInactivated,
RamReadAddr => 0,
RamAddr => 0,
RamWriteAddr => 0,
RamWe => cInactivated,
RamData => (others => '0'));
 
signal R : aReg := cDefaultReg;
signal NextR : aReg;
signal ReceivedContent : aSdCmdContent;
signal oReceivedContentValid : std_ulogic;
signal ReceivedData : std_ulogic_vector(511 downto 0);
signal ReceivedDataValid : std_ulogic;
signal RamData : std_ulogic_vector(31 downto 0);
 
begin
 
oDigitAdr <= "101"; -- DIGIT_6
Reg : process (iClk) is
begin
if (rising_edge(iClk)) then
RstSync(0) <= inResetAsync;
RstSync(1) <= not RstSync(1);
end if;
end process Reg;
 
NoDebug_inst: if gDebug = false generate
oTx <= '1';
end generate;
oDigitAdr <= "101"; -- DIGIT_6
oTx <= '1';
 
Debug_inst: if gDebug = true generate
oTx <= oRs232Tx.Tx;
 
iRs232Tx.Transmit <= cActivated;
iRs232Tx.Data <= R.Data;
iRs232Tx.DataAvailable <= R.DataAvailable;
 
-- Send ReceivedContent via Rs232
Rs232_Send : process (iClk, inResetAsync)
begin
if (inResetAsync = cnActivated) then
R <= cDefaultReg;
 
elsif (iClk'event and iClk = cActivated) then
R <= NextR;
 
end if;
end process Rs232_Send;
 
Rs232_comb : process (oRs232Tx.DataWasRead, ReceivedContent, oReceivedContentValid, ReceivedDataValid, ReceivedData, RamData, R)
variable NextWrite : std_ulogic;
 
begin
NextR <= R;
NextR.RamWe <= cInactivated;
NextWrite := cActivated;
 
case R.WriteState is
when idle =>
NextR.WriteCounter <= 0;
NextWrite := cInactivated;
 
if (ReceivedDataValid = cActivated) then
NextR.WriteState <= data;
elsif (oReceivedContentValid = cActivated) then
NextR.WriteState <= id;
end if;
 
when id =>
NextR.RamWriteAddr <= R.RamWriteAddr + 1;
NextR.RamAddr <= R.RamWriteAddr + 1;
NextR.RamData <= X"000000" & "00" & ReceivedContent.id;
NextR.RamWe <= cActivated;
NextR.WriteState <= arg;
 
when arg =>
NextR.RamWriteAddr <= R.RamWriteAddr + 1;
NextR.RamAddr <= R.RamWriteAddr + 1;
NextR.RamData <= ReceivedContent.arg;
NextR.RamWe <= cActivated;
NextR.WriteState <= idle;
 
when data =>
NextR.RamWriteAddr <= R.RamWriteAddr + 1;
NextR.RamAddr <= R.RamWriteAddr + 1;
NextR.RamData <= ReceivedData((15-R.WriteCounter) * 32 + 31 downto (15 - R.WriteCounter) * 32);
NextR.RamWe <= cActivated;
 
if (R.WriteCounter = 15) then
NextR.WriteState <= idle;
else
NextR.WriteCounter <= R.WriteCounter + 1;
end if;
 
when others =>
report "Unhandled state" severity error;
end case;
 
case R.ReadState is
when waitforchange =>
NextR.DataAvailable <= cInactivated;
 
if (R.RamReadAddr /= R.RamWriteAddr and NextWrite = cInactivated) then
NextR.RamReadAddr <= R.RamReadAddr + 1;
NextR.RamAddr <= R.RamReadAddr + 1;
NextR.ReadCounter <= 0;
NextR.ReadState <= send;
end if;
 
when send =>
NextR.DataAvailable <= cActivated;
 
if (R.ReadCounter = 0) then
NextR.Data <= RamData((3-R.ReadCounter)*8 + 7 downto (3-R.ReadCounter)*8);
NextR.RamBuffer <= RamData;
else
NextR.Data <= R.RamBuffer((3-R.ReadCounter)*8 + 7 downto (3-R.ReadCounter)*8);
end if;
 
if (oRs232Tx.DataWasRead = cActivated) then
NextR.DataAvailable <= cInactivated;
 
if (R.ReadCounter = 3) then
NextR.ReadState <= waitforchange;
else
NextR.ReadCounter <= R.ReadCounter + 1;
end if;
end if;
 
when others =>
report "Invalid state" severity error;
end case;
 
end process Rs232_comb;
 
Rs232Tx_inst : entity work.Rs232Tx
port map(
iClk => iClk,
inResetAsync => inResetAsync,
iRs232Tx => iRs232Tx,
oRs232Tx => oRs232Tx);
 
StrobeGen_Rs232 : entity work.StrobeGen
generic map (
gClkFrequency => cClkFreq,
gStrobeCycleTime => 1 sec / cBaudRate)
port map (
iClk => iClk,
inResetAsync => inResetAsync,
oStrobe => iRs232Tx.BitStrobe);
 
Ram_inst : entity work.SinglePortedRam
generic map(
gDataWidth => 32,
gAddrWidth => 7
)
port map (
iClk => iClk,
iAddr => R.RamAddr,
iData => R.RamData,
iWe => R.RamWe,
oData => RamData
);
 
end generate;
 
Gen25MHz: if gClkFreq = 25E6 generate
-- Configure clock to 25MHz
Ics307Configurator_inst : entity work.Ics307Configurator(Rtl)
generic map(
gCrystalLoadCapacitance_C => cCrystalLoadCapacitance_C_25MHz,
gReferenceDivider_RDW => cReferenceDivider_RDW_25MHz,
gVcoDividerWord_VDW => cVcoDividerWord_VDW_25MHz,
gOutputDivide_S => cOutputDivide_S_25MHz,
gClkFunctionSelect_R => cClkFunctionSelect_R_25MHz,
gOutputDutyCycleVoltage_TTL => cOutputDutyCycleVoltage_TTL_25MHz
)
port map(
iClk => iClk,
inResetAsync => inResetAsync,
oSclk => oIcs307Sclk,
oData => oIcs307Data,
oStrobe => oIcs307Strobe
);
end generate;
 
Gen50MHz: if gClkFreq = 50E6 generate
-- Configure clock to 50MHz
Ics307Configurator_inst : entity work.Ics307Configurator(Rtl)
generic map(
gCrystalLoadCapacitance_C => cCrystalLoadCapacitance_C_50MHz,
gReferenceDivider_RDW => cReferenceDivider_RDW_50MHz,
gVcoDividerWord_VDW => cVcoDividerWord_VDW_50MHz,
gOutputDivide_S => cOutputDivide_S_50MHz,
gClkFunctionSelect_R => cClkFunctionSelect_R_50MHz,
gOutputDutyCycleVoltage_TTL => cOutputDutyCycleVoltage_TTL_50MHz
)
port map(
iClk => iClk,
inResetAsync => inResetAsync,
oSclk => oIcs307Sclk,
oData => oIcs307Data,
oStrobe => oIcs307Strobe
);
end generate;
 
Gen100MHz: if gClkFreq = 100E6 generate
Gen100MHz: if gClkFrequency = 100E6 generate
-- Configure clock to 100MHz
Ics307Configurator_inst : entity work.Ics307Configurator(Rtl)
generic map(
300,20 → 96,34
 
SDTop_inst : entity work.SdTop(Rtl)
generic map (
gClkFrequency => cClkFreq,
gClkFrequency => gClkFrequency,
gHighSpeedMode => true
)
port map (
iClk => iClk,
inResetAsync => inResetAsync,
ioCmd => ioCmd,
oSclk => oSclk,
ioData => ioData,
oReceivedContent => ReceivedContent,
oReceivedContentValid => oReceivedContentValid,
oReceivedData => ReceivedData,
oReceivedDataValid => ReceivedDataValid,
oLedBank => oLedBank
iWbClk => iClk,
iRstSync => RstSync(1),
 
iCyc => iCyc,
iLock => iLock,
iStb => iStb,
iWe => iWe,
iCti => iCti,
iBte => iBte,
iSel => iSel,
iAdr => iAdr,
iDat => iDat,
 
oDat => oDat,
oAck => oAck,
oErr => oErr,
oRty => oRty,
 
iSdClk => iClk,
inResetAsync => inResetAsync,
ioCmd => ioCmd,
oSclk => oSclk,
ioData => ioData,
oLedBank => oLedBank
);
 
end architecture Rtl;
/src/grpSd/unitSdTop/src/SdTop-Rtl-ea.vhdl
9,15 → 9,38
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Global.all;
use work.Wishbone.all;
use work.Sd.all;
use work.SdWb.all;
 
entity SdTop is
generic (
gClkFrequency : natural := 25E6;
gUseSameClocks : boolean := true;
gClkFrequency : natural := 100E6;
gHighSpeedMode : boolean := true
);
port (
iClk : in std_ulogic;
-- Wishbone interface
iWbClk : in std_ulogic;
iRstSync : in std_ulogic;
 
iCyc : in std_ulogic;
iLock : in std_ulogic;
iStb : in std_ulogic;
iWe : in std_ulogic;
iCti : in std_ulogic_vector(2 downto 0);
iBte : in std_ulogic_vector(1 downto 0);
iSel : in std_ulogic_vector(0 downto 0);
iAdr : in std_ulogic_vector(6 downto 4);
iDat : in std_ulogic_vector(31 downto 0);
 
oDat : out std_ulogic_vector(31 downto 0);
oAck : out std_ulogic;
oErr : out std_ulogic;
oRty : out std_ulogic;
 
-- Sd interface
iSdClk : in std_ulogic;
inResetAsync : in std_ulogic;
 
-- SD Card
26,10 → 49,6
ioData : inout std_logic_vector(3 downto 0);
 
-- Status
oReceivedContent : out aSdCmdContent;
oReceivedContentValid : out std_ulogic;
oReceivedData : out std_ulogic_vector(511 downto 0);
oReceivedDataValid : out std_ulogic;
oLedBank : out aLedBank
);
 
45,119 → 64,91
signal SdDataToRam : aSdDataToRam;
signal SdControllerToDataRam : aSdControllerToRam;
signal SdControllerFromDataRam : aSdControllerFromRam;
signal SdWbSlaveToController : aSdWbSlaveToSdController;
signal SdWbSlaveFromController : aSdControllerToSdWbSlave;
 
signal SdStrobe : std_ulogic;
signal SdStrobe25MHz : std_ulogic;
signal SdStrobe50MHz : std_ulogic;
signal HighSpeed : std_ulogic;
 
signal iCmd : aiSdCmd;
signal oCmd : aoSdCmd;
signal iData : aiSdData;
signal oData : aoSdData;
signal iCmd : aiSdCmd;
signal oCmd : aoSdCmd;
signal iData : aiSdData;
signal oData : aoSdData;
 
signal Sclk : std_ulogic;
signal Counter : natural range 0 to 3;
 
signal iWbCtrl : aWbSlaveCtrlInput;
signal oWbCtrl : aWbSlaveCtrlOutput;
signal iWbDat : aSdWbSlaveDataInput;
signal oWbDat : aSdWbSlaveDataOutput;
begin
 
Reg : process (iClk, inResetAsync)
begin
if (inResetAsync = cnActivated) then
iCmd.Cmd <= '1';
iData.Data <= (others => '1');
elsif (rising_edge(iClk)) then
iCmd.Cmd <= ioCmd;
iData.Data <= std_ulogic_vector(ioData);
end if;
end process Reg;
 
ioCmd <= oCmd.Cmd when oCmd.En = cActivated else 'Z';
Gen_data : for i in 0 to 3 generate
ioData(i) <= oData.Data(i) when oData.En(i) = cActivated else 'Z';
end generate;
 
Sclk100MHz: if gClkFrequency = 100E6 generate
-- map wishbone signals to internal signals
iWbCtrl <= (
Cyc => iCyc,
Lock => iLock,
Stb => iStb,
We => iWe,
Cti => iCti,
Bte => iBte
);
 
ClkDivider : process (iClk, inResetAsync)
begin
if (inResetAsync = cnActivated) then
Counter <= 0;
Sclk <= cInactivated;
oAck <= oWbCtrl.Ack;
oErr <= oWbCtrl.Err;
oRty <= oWbCtrl.Rty;
oDat <= oWbDat.Dat;
 
elsif (rising_edge(iClk)) then
if (HighSpeed = cActivated) then
if (Counter = 0 or Counter = 2) then
Sclk <= cActivated;
else
Sclk <= cInactivated;
end if;
else
if (Counter = 0 or Counter = 1) then
Sclk <= cActivated;
else
Sclk <= cInactivated;
end if;
end if;
iWbDat <= (
Sel => iSel,
Adr => iAdr,
Dat => iDat
);
 
if (Counter < 3) then
Counter <= Counter + 1;
else
Counter <= 0;
end if;
end if;
end process ClkDivider;
SdWbSlave_inst : entity work.SdWbSlave
port map (
iClk => iWbClk,
iRstSync => iRstSync,
 
oSclk <= not Sclk;
SdStrobe <= SdStrobe25MHz when HighSpeed = cInactivated else SdStrobe50MHz;
SdStrobe_inst25: entity work.StrobeGen(Rtl)
generic map (
gClkFrequency => gClkFrequency,
gStrobeCycleTime => 1 sec / 25E6)
port map (
iClk => iClk,
inResetAsync => inResetAsync,
oStrobe => SdStrobe25MHz);
SdStrobe_inst50: entity work.StrobeGen(Rtl)
generic map (
gClkFrequency => gClkFrequency,
gStrobeCycleTime => 1 sec / 50E6)
port map (
iClk => iClk,
inResetAsync => inResetAsync,
oStrobe => SdStrobe50MHz);
end generate;
-- wishbone
iWbCtrl => iWbCtrl,
oWbCtrl => oWbCtrl,
iWbDat => iWbDat,
oWbDat => oWbDat,
-- To sd controller
iController => SdWbSlaveFromController,
oController => SdWbSlaveToController
);
 
Sclk50Mhz: if gClkFrequency = 50E6 generate
 
oSclk <= not Sclk;
Sclk <= SdStrobe25MHz when HighSpeed = cInactivated else iClk;
SdStrobe <= SdStrobe25MHz when HighSpeed = cInactivated else cActivated;
SdStrobe_inst: entity work.StrobeGen(Rtl)
generic map (
gClkFrequency => gClkFrequency,
gStrobeCycleTime => 1 sec / 25E6)
port map (
iClk => iClk,
inResetAsync => inResetAsync,
oStrobe => SdStrobe25MHz);
end generate;
SdClockMaster_inst: entity work.SdClockMaster
generic map (
gClkFrequency => gClkFrequency
)
port map (
iClk => iSdClk,
iRstSync => iRstSync,
iHighSpeed => HighSpeed,
oSdStrobe => SdStrobe,
oSdCardClk => oSClk
);
 
Sclk25MHz: if gClkFrequency = 25E6 generate
SdCardSynchronizer_inst : entity work.SdCardSynchronizer
port map (
 
oSclk <= not iClk;
SdStrobe <= cActivated;
iClk => iSdClk,
iRstSync => iRstSync,
iCmd => ioCmd,
iData => ioData,
oCmdSync => iCmd.Cmd,
oDataSync => iData.Data
 
end generate;
);
 
oReceivedContent <= SdCmdToController.Content;
oReceivedContentValid <= SdCmdToController.Valid;
oReceivedDataValid <= SdDataToController.Valid;
 
SdController_inst: entity work.SdController(Rtl)
generic map (
gClkFrequency => gClkFrequency,
164,7 → 155,7
gHighSpeedMode => gHighSpeedMode
)
port map (
iClk => iClk,
iClk => iSdClk,
inResetAsync => inResetAsync,
oHighSpeed => HighSpeed,
iSdCmd => SdCmdToController,
173,12 → 164,14
oSdData => SdDataFromController,
iDataRam => SdControllerFromDataRam,
oDataRam => SdControllerToDataRam,
oSdWbSlave => SdWbSlaveFromController,
iSdWbSlave => SdWbSlaveToController,
oLedBank => oLedBank
);
 
SdCmd_inst: entity work.SdCmd(Rtl)
port map (
iClk => iClk,
iClk => iSdClk,
inResetAsync => inResetAsync,
iStrobe => SdStrobe,
iFromController => SdCmdFromController,
189,7 → 182,7
 
SdData_inst: entity work.SdData
port map (
iClk => iClk,
iClk => iSdClk,
inResetAsync => inResetAsync,
iStrobe => SdStrobe,
iSdDataFromController => SdDataFromController,
206,7 → 199,7
gAddrWidth => 7
)
port map (
iClk => iClk,
iClk => iSdClk,
iAddrRW => SdDataToRam.Addr,
iDataRW => SdDataToRam.Data,
iWeRW => SdDataToRam.We,
/src/grpSd/unitSdVerificationTestbench/Files.tcl
3,7 → 3,10
Sd Sd
Crc CRCs
Rs232 Rs232
Components Ics307Values}
Components Ics307Values
Wishbone Wishbone
Sd SdWb
}
 
set units {Crc Crc {Rtl}
Sd SdCmd {Rtl}
13,6 → 16,9
Memory SimpleDualPortedRam {Rtl}
Memory SinglePortedRam {Rtl}
StrobesClocks StrobeGen {Rtl}
Sd SdWbSlave {Rtl}
Sd SdClockMaster {Rtl}
Sd SdCardSynchronizer {Rtl}
Sd SdTop {Rtl}
Rs232 Rs232Tx {Rtl}
Components Ics307Configurator {Rtl}
/src/grpSd/unitSdController/src/SdController-Rtl-a.vhdl
92,7 → 92,7
end if;
end process Regs;
 
Comb : process (iSdCmd, iSdData, iDataRam, Timeout, R)
Comb : process (iSdCmd, iSdData, iDataRam, iSdWbSlave, Timeout, R)
variable ocr : aSdRegOCR;
variable arg : aSdCmdArg;
variable NextRegion : aRegion;
/src/grpSd/unitSdController/src/SdController-e.vhdl
12,8 → 12,10
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.Global.all;
use work.Sd.all;
use work.SdWb.all;
 
entity SdController is
generic (
39,6 → 41,10
iDataRam : in aSdControllerFromRam;
oDataRam : out aSdControllerToRam;
 
-- SdWbSlave
iSdWbSlave : in aSdWbSlaveToSdController;
oSdWbSlave : out aSdControllerToSdWbSlave;
 
-- Status
oLedBank : out aLedBank
);
/src/grpSd/unitSdCardSynchronizer/src/SdCardSynchronizer-Rtl-ea.vhdl
0,0 → 1,73
--
-- Title: SdCardSynchronizer
-- File: SdCardSynchronizer-Rtl-ea.vhdl
-- Author: Copyright 2010: Rainer Kastl
-- Standard: VHDL'93
--
-- Description: Synchronizes the SD Card inputs
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.global.all;
 
entity SdCardSynchronizer is
generic (
gSyncCount : natural := 1
);
port (
 
iClk : in std_ulogic;
iRstSync : in std_ulogic;
iCmd : in std_logic;
iData : in std_logic_vector(3 downto 0);
oCmdSync : out std_ulogic;
oDataSync : out std_ulogic_vector(3 downto 0)
 
);
end entity SdCardSynchronizer;
 
architecture Rtl of SdCardSynchronizer is
 
type aDataSync is array (0 to gSyncCount - 1) of std_ulogic_vector(3 downto 0);
 
signal CmdSync : std_ulogic_vector(gSyncCount - 1 downto 0);
signal DataSync : aDataSync;
 
begin
 
-- Registers
Reg : process (iClk, iRstSync)
begin
if (rising_edge(iClk)) then
-- synchronous reset
if (iRstSync = cActivated) then
 
CmdSync <= (others => '0');
DataSync <= (others => (others => '0'));
 
else
 
-- register input data
CmdSync(0) <= iCmd;
DataSync(0) <= std_ulogic_vector(iData);
 
-- additional synchronization FFs
for i in 1 to gSyncCount - 1 loop
 
CmdSync(i) <= CmdSync(i - 1);
DataSync(i) <= DataSync(i - 1);
 
end loop;
end if;
end if;
end process Reg;
 
-- output the last registers
 
oCmdSync <= CmdSync(gSyncCount - 1);
oDataSync <= DataSync(gSyncCount - 1);
 
end architecture Rtl;
/src/grpSd/unitSdClockMaster/src/SdClockMaster-Rtl-a.vhdl
0,0 → 1,78
--
-- Title:
-- File: SdClockMaster-Rtl-a.vhdl
-- Author: Copyright 2010: Rainer Kastl
-- Standard: VHDL'93
--
-- Description: Architecture for SdClockMaster
--
 
architecture Rtl of SdClockMaster is
 
signal SdClk : std_ulogic;
signal Counter : natural range 0 to 3;
signal SdStrobe25MHz : std_ulogic;
signal SdStrobe50MHz : std_ulogic;
 
begin
 
SdClk100MHz: if gClkFrequency = 100E6 generate
 
ClkDivider : process (iClk, iRstSync)
begin
if (rising_edge(iClk)) then
 
-- synchronous reset
if (iRstSync = cActivated) then
Counter <= 0;
SdClk <= cInactivated;
else
 
if (iHighSpeed = cActivated) then
if (Counter = 0 or Counter = 2) then
SdClk <= cActivated;
else
SdClk <= cInactivated;
end if;
else
if (Counter = 0 or Counter = 1) then
SdClk <= cActivated;
else
SdClk <= cInactivated;
end if;
end if;
 
if (Counter < 3) then
Counter <= Counter + 1;
else
Counter <= 0;
end if;
end if;
end if;
end process ClkDivider;
 
oSdCardClk <= not SdClk;
oSdStrobe <= SdStrobe25MHz when iHighSpeed = cInactivated else SdStrobe50MHz;
 
SdStrobe_inst25: entity work.StrobeGen(Rtl)
generic map (
gClkFrequency => gClkFrequency,
gStrobeCycleTime => 1 sec / 25E6)
port map (
iClk => iClk,
iRstSync => iRstSync,
oStrobe => SdStrobe25MHz);
 
SdStrobe_inst50: entity work.StrobeGen(Rtl)
generic map (
gClkFrequency => gClkFrequency,
gStrobeCycleTime => 1 sec / 50E6)
port map (
iClk => iClk,
iRstSync => iRstSync,
oStrobe => SdStrobe50MHz);
 
end generate;
 
end architecture Rtl;
 
/src/grpSd/unitSdClockMaster/src/SdClockMaster-e.vhdl
0,0 → 1,35
--
-- Title:
-- File: SdClockMaster-e.vhdl
-- Author: Copyright 2010: Rainer Kastl
-- Standard: VHDL'93
--
-- Description: Handles Sclk generation and strobe signal generation
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
use work.global.all;
 
entity SdClockMaster is
generic (
gClkFrequency : natural := 100E6
);
port (
iClk : in std_ulogic;
iRstSync : in std_ulogic;
iHighSpeed : in std_ulogic;
oSdStrobe : out std_ulogic;
oSdCardClk : out std_ulogic
);
 
begin
 
assert (gClkFrequency = 100E6)
report "SdCore needs an SdClk with 100 MHz"
severity failure;
 
end entity SdClockMaster;
 
/src/grpStrobesClocks/unitStrobeGen/src/StrobeGen-Rtl-a.vhdl
14,25 → 14,31
-------------------------------------------------------------------------------
architecture Rtl of StrobeGen is
 
constant max : natural := gClkFrequency/(1 sec/ gStrobeCycleTime);
constant cBitWidth : natural := LogDualis(max); -- Bitwidth
signal Counter : unsigned (cBitWidth - 1 downto 0) := (others => '0');
constant max : natural := gClkFrequency/(1 sec/ gStrobeCycleTime);
constant cBitWidth : natural := LogDualis(max); -- Bitwidth
signal Counter : unsigned (cBitWidth - 1 downto 0) := (others => '0');
 
begin -- architecture Rtl
 
StateReg : process (iClk, inResetAsync) is
begin -- process StateReg
if inResetAsync = cnActivated then -- asynchronous reset (active low)
Counter <= (others => '0');
oStrobe <= cInactivated;
elsif iClk'event and iClk = cActivated then -- rising clock edge
Counter <= Counter + 1;
if Counter < max - 1 then
oStrobe <= cInactivated;
else
oStrobe <= cActivated;
Counter <= TO_UNSIGNED(0, cBitWidth);
end if;
end if;
end process StateReg;
StateReg : process (iClk, inResetAsync) is
begin -- process StateReg
if inResetAsync = cnActivated then -- asynchronous reset (active low)
Counter <= (others => '0');
oStrobe <= cInactivated;
elsif iClk'event and iClk = cActivated then -- rising clock edge
if (iRstSync = cActivated) then
Counter <= (others => '0');
oStrobe <= cInactivated;
 
else
Counter <= Counter + 1;
if Counter < max - 1 then
oStrobe <= cInactivated;
else
oStrobe <= cActivated;
Counter <= TO_UNSIGNED(0, cBitWidth);
end if;
end if;
end if;
end process StateReg;
end architecture Rtl;
/src/grpStrobesClocks/unitStrobeGen/src/StrobeGen-e.vhdl
29,8 → 29,9
 
port (
-- Sequential logic inside this unit
iClk : in std_ulogic;
inResetAsync : in std_ulogic;
iClk : in std_ulogic;
inResetAsync : in std_ulogic := '1';
iRstSync : in std_ulogic := '0';
 
-- Strobe with the above given cycle time
oStrobe : out std_ulogic);

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