OpenCores
URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /sdhc-sc-core/trunk
    from Rev 135 to Rev 136
    ↔ Reverse comparison
  •

Rev 135 → Rev 136

/src/grpSd/unitSdCmd/src/SdCmd-Rtl-ea.vhdl
21,6 → 21,7
port (
iClk : in std_ulogic; -- Clk, rising edge
inResetAsync : in std_ulogic; -- Reset, asynchronous active low
 
iStrobe : in std_ulogic; -- Strobe to send data
 
iFromController : in aSdCmdFromController;
36,6 → 37,7
 
type aSdCmdState is (idle, sending, receiving);
type aRegion is (startbit, transbit, cmdid, arg, cid, crc, endbit, waitstate);
subtype aCounter is unsigned(integer(log2(real(128))) - 1 downto 0);
 
type aRegSet is record
54,8 → 56,8
Cid => cDefaultSdRegCID);
 
type aOutputRegSet is record
Controller : aSdCmdToController;
Cmd : aoSdCmd;
Controller : aSdCmdToController;
Cmd : aoSdCmd;
end record aOutputRegSet;
 
constant cDefaultOutputRegSet : aOutputRegSet := (
149,14 → 151,18
when idle =>
-- Start receiving or start transmitting
if (iCmd.Cmd = cSdStartBit) then
-- Start receiving
ShiftIntoCrc(iCmd.Cmd);
 
NextR.ReceivedToken.startbit <= iCmd.Cmd;
NextR.State <= receiving;
NextR.Region <= transbit;
NextR.State <= receiving;
NextR.Region <= transbit;
 
elsif (iFromController.Valid = cActivated) then
NextR.State <= sending;
-- Start sending
NextR.State <= sending;
NextR.Region <= startbit;
 
end if;
 
when sending =>
187,17 → 193,17
NextR.Counter <= R.Counter - 1;
 
else
NextR.Region <= endbit;
NextR.Region <= endbit;
NextO.Controller.Ack <= cActivated;
end if;
 
when endbit =>
NextO.Cmd.Cmd <= cSdEndBit;
NextR.Region <= waitstate;
NextO.Cmd.Cmd <= cSdEndBit;
NextR.Region <= waitstate;
 
when waitstate =>
NextO.Cmd.En <= cInactivated;
NextR.State <= idle;
NextR.State <= idle;
NextR.Region <= startbit;
 
when others =>
/src/grpSd/unitSdCmd/src/tbSdCmd-Bhv-ea.vhdl
18,13 → 18,15
architecture Bhv of tbSdCmd is
 
constant cClkPeriod : time := 1 sec / gClkFrequency;
signal Clk : std_ulogic := cInactivated;
signal Finished : std_ulogic := cInactivated;
signal nResetAsync : std_ulogic := cnActivated;
signal ToCmd : aSdCmdFromController;
signal FromCmd : aSdCmdToController;
signal Cmd : std_logic;
signal Clk : std_ulogic := cInactivated;
signal Finished : std_ulogic := cInactivated;
signal nResetAsync : std_ulogic := cnActivated;
 
 
signal ToCmd : aSdCmdFromController;
signal FromCmd : aSdCmdToController;
signal Cmd : std_ulogic;
 
signal sentCmd : std_ulogic_vector(47 downto 0) := (others => 'U');
signal counter : integer := 0;
signal save : std_ulogic := cInactivated;
73,7 → 75,7
iStrobe => Strobe,
iFromController => ToCmd,
oToController => FromCmd,
ioCmd => Cmd
iCmd => Cmd
);
 
Strobe_inst: entity work.StrobeGen(Rtl)
/src/grpSd/unitSdData/src/SdData-Rtl-a.vhdl
15,8 → 15,6
 
-- all registers
type aReg is record
-- state, region and counters
 
State : aState;
Region : aRegion;
Counter : aCounter;
24,7 → 22,7
Mode : aSdDataBusMode; -- standard or wide SD mode
 
Word : aWord; -- temporary save for data to write to the read fifo
WordInvalid : std_ulogic; -- after starting receiving we have to wait for word to be valid before it can be written to the read fifo
WordInvalid : std_ulogic; -- after starting receiving we have to wait for the word to be valid before it can be written to the read fifo
 
-- outputs
Data : aoSdData;
73,6 → 71,7
alias RBitC is R.Counter(LogDualis(8)-1 downto 0);
alias RByteC is R.Counter(LogDualis(4)+LogDualis(8)-1 downto LogDualis(8));
alias RWordC is R.Counter(R.Counter'high downto LogDualis(4)+LogDualis(8));
alias RBitInWordC is R.Counter(LogDualis(32)-1 downto 0);
 
begin
 
108,7 → 107,7
end process Regs;
 
-- Calculate the next state and output
Comb : process (iData.Data, iSdDataFromController, CrcIn, iReadWriteFifo, iWriteReadFifo, R)
Comb : process (iData, iSdDataFromController, CrcIn, iReadWriteFifo, iWriteReadFifo, R)
 
--------------------------------------------------------------------------------
-- Handle accessing the fifo
123,6 → 122,7
NextR.Counter <= R.Counter;
req <= cInactivated;
else
-- enable request and continue transfer with the sd card
NextR.DisableSdClk <= cInactivated;
req <= cActivated;
end if;
147,7 → 147,7
end procedure SendBitsAndShiftIntoCrc;
 
--------------------------------------------------------------------------------
-- Calculate the next counters and region
-- Calculate the next counter and region
-- Handles loading next data from fifo or writing data to fifo as well
--------------------------------------------------------------------------------
procedure CalcNextAndHandleData (constant send : boolean) is
163,12 → 163,12
end if;
 
if (RBitC = BitEnd) then
-- Byte finished
-- Byte finished, switch to next byte starting with MSBit
NextR.Counter <= R.Counter + (16 - BitDec);
 
if (RByteC = 3) then
-- Word finished
NextR.WordInvalid <= cInactivated;
NextR.WordInvalid <= cInactivated; -- received words are no longer invalid
 
if (RWordC = 127) then
-- whole block finished, send crc next
177,24 → 177,24
 
else
if (send = true) then
-- save next word from fifo
-- save next word to send from fifo
NextR.Word <= iReadWriteFifo.q;
end if;
end if;
end if;
else
NextR.Counter <= R.Counter - BitDec;
NextR.Counter <= R.Counter - BitDec; -- switch to next bits (MSBit to LSBit)
end if;
 
if (send = true) then
if ((RBitC = BitEnd + BitDec and RByteC = 3 and RWordC < 127)) then
-- request next word from fifo
-- current word almost sent, request next word to send from fifo
HandleFifoAccess(iReadWriteFifo.rdempty, NextR.ReadWriteFifo.rdreq);
 
end if;
else
if (RByteC = 0 and RBitC = 7 and R.WordInvalid = cInactivated) then
-- save word to ram
-- received word is valid, save it to ram
NextR.WriteReadFifo.data <= R.Word;
HandleFifoAccess(iWriteReadFifo.wrfull, NextR.WriteReadFifo.wrreq);
end if;
209,6 → 209,8
variable curHighAddr : integer;
begin
-- calculate current address (of the high bit in case of wide mode)
-- widewidth receiving counts from an offset to 4096
-- and the bit counter is reversed
curHighAddr := (127 - to_integer(RWordC)) * 32 + (3 - to_integer(RByteC)) * 8 + to_integer(RBitC);
 
if (R.Mode = standard) then
248,21 → 250,18
 
case R.State is
when idle =>
-- check if card signals that it is busy
-- check if card signals that it is busy (the controller has to enable this check)
if (iSdDataFromController.CheckBusy = cActivated and iData.Data(0) = cInactivated) then
NextR.Controller.Busy <= cActivated;
 
elsif (R.Mode = wide and iData.Data = cSdStartBits) or
(R.Mode = standard and iData.Data(0) = cSdStartBit) then
 
elsif (R.Mode = wide and iData.Data = cSdStartBits) or (R.Mode = standard and iData.Data(0) = cSdStartBit) then
-- start receiving
 
NextR.Region <= data;
NextR.State <= receive;
NextR.Counter <= to_unsigned(7,aCounter'length);
NextR.WordInvalid <= cActivated;
 
-- which response is expected?
-- which kind of response is expected?
if (iSdDataFromController.DataMode = widewidth) then
if (iSdDataFromController.ExpectBits = ScrBits) then
NextR.Counter <= to_unsigned(cScrBitsCount, aCounter'length);
272,15 → 271,16
end if;
 
elsif (iSdDataFromController.Valid = cActivated) then
-- sending requested by controller
 
case iReadWriteFifo.rdempty is
when cActivated =>
-- no data is available to send -> stall
report "Fifo empty, waiting for data" severity note;
NextR.DisableSdClk <= cActivated;
 
when cInactivated =>
-- start sending
 
-- data is available, start sending
NextR.State <= send;
NextR.Region <= startbit;
NextR.ReadWriteFifo.rdreq <= cActivated;
291,7 → 291,7
report "rdempty invalid" severity error;
end case;
else
-- switch between standard and wide mode
-- switch between standard and wide mode only if nothing else is going on
NextR.Mode <= iSdDataFromController.Mode;
end if;
 
315,7 → 315,7
SendBitsAndShiftIntoCrc(cSdStartBits);
NextR.Region <= data;
 
-- save data from fifo
-- save data to send from fifo
NextR.Word <= iReadWriteFifo.q;
 
when data =>
322,11 → 322,11
case R.Mode is
when wide =>
for i in 0 to 3 loop
temp(i) := R.Word(to_integer(R.Counter(4 downto 0)) - i);
temp(i) := R.Word(to_integer(RBitInWordC) - i);
end loop;
 
when standard =>
temp := "---" & R.Word(to_integer(R.Counter(4 downto 0)));
temp := "---" & R.Word(to_integer(RBitInWordC));
 
when others =>
temp := "XXXX";
362,11 → 362,11
-- save received data to temporary word register
case R.Mode is
when standard =>
NextR.Word(to_integer(R.Counter(4 downto 0))) <= iData.Data(0);
NextR.Word(to_integer(RBitInWordC)) <= iData.Data(0);
 
when wide =>
for i in 0 to 3 loop
NextR.Word(to_integer(R.Counter(4 downto 0)) - i) <= iData.Data(3 - i);
NextR.Word(to_integer(RBitInWordC) - i) <= iData.Data(3 - i);
end loop;
 
when others =>
376,7 → 376,7
ShiftIntoCrc(std_ulogic_vector(iData.Data));
CalcNextAndHandleData(false);
 
-- check responses
-- check responses
if (iSdDataFromController.DataMode = widewidth) then
if (iSdDataFromController.ExpectBits = ScrBits) then
if (IsBitAddrInRangeWideWidth(cWideModeBitAddr)) then
394,7 → 394,7
end if;
 
when crc =>
-- save last word to ram
-- save last word to ram
HandleFifoAccess(iWriteReadFifo.wrfull, NextR.WriteReadFifo.wrreq);
NextR.WriteReadFifo.data <= R.Word;
 
408,7 → 408,7
end if;
 
when endbit =>
-- in standard mode all unused crcs have to be correct, because no data was shifted in
-- in standard mode all unused crcs are correct, because no data was shifted in
if (CrcIn.Correct = "1111") then
NextR.Controller.Valid <= cActivated;
else
428,8 → 428,7
 
end process Comb;
 
CrcDataIn <= (others => CrcOut.DataIn) when R.Mode = wide else
"000" & CrcOut.DataIn;
CrcDataIn <= (others => CrcOut.DataIn) when R.Mode = wide else "000" & CrcOut.DataIn;
 
crcs: for idx in 3 downto 0 generate
 
/src/grpSd/unitTbdSd/Files.tcl
24,6 → 24,7
Rs232 Rs232Tx {Rtl}
Components Ics307Configurator {Rtl}
StrobesClocks StrobeGen {Rtl}
Sd TestWbMaster {Rtl}
Sd TbdSd {Rtl}}
 
 
/src/grpSd/unitTbdSd/src/TbdSd-Rtl-ea.vhdl
61,6 → 61,8
signal oErr : std_ulogic;
signal oRty : std_ulogic;
 
signal ErrorLed, DoneLed : std_ulogic;
 
begin
 
Reg : process (iClk) is
126,5 → 128,25
oLedBank => oLedBank
);
 
TestWbMaster_inst : entity work.TestWbMaster
port map (
CLK_I => iClk,
RST_I => RstSync(1),
ERR_I => oErr,
RTY_I => oRty,
ACK_I => oAck,
DAT_I => oDat,
CYC_O => iCyc,
STB_O => iStb,
WE_O => iWe,
CTI_O => iCti,
BTE_O => iBte,
ADR_O => iAdr,
DAT_O => iDat,
SEL_O => iSel,
ERR_O => ErrorLed,
DON_O => DoneLed
);
 
end architecture Rtl;
 
/src/grpSd/unitSdVerificationTestbench/sim/modelsim.ini
186,6 → 186,28
; Turn off reset state transitions in FSM.
; FsmResetTrans = 0
 
NoDebug = 0
CheckSynthesis = 0
NoVitalCheck = 0
Optimize_1164 = 1
NoVital = 0
Quiet = 0
Show_source = 0
DisableOpt = 0
ZeroIn = 0
CoverageNoSub = 0
NoCoverage = 0
Coverage = sbcef
CoverCells = 0
CoverExcludeDefault = 1
CoverageFEC = 1
CoverageShortCircuit = 0
CoverOpt = 3
Show_Warning1 = 1
Show_Warning2 = 1
Show_Warning3 = 1
Show_Warning4 = 1
Show_Warning5 = 1
[vlog]
; Turn off inclusion of debugging info within design units.
; Default is to include debugging info.
410,6 → 432,24
; Default is true (1).
; PrintSVPackageLoadingAttribute = 1
 
vlog95compat = 0
Vlog01Compat = 0
Svlog = 0
Coverage = sbcef
CoverCells = 0
CoverExcludeDefault = 1
CoverageFEC = 0
CoverageShortCircuit = 0
CoverOpt = 3
OptionFile = /home/draugdel/SD-CORE/src/grpSd/unitSdVerificationTestbench/sim/vlog.opt
Quiet = 0
Show_source = 0
Protect = 0
NoDebug = 0
Hazard = 0
UpCase = 0
DisableOpt = 0
ZeroIn = 0
[sccom]
; Enable use of SCV include files and library. Default is off.
; UseScv = 1
430,6 → 470,10
; Enable use of SC_MS include files and library. Default is off.
; UseScMs = 1
 
UseScv = 0
UseScMs = 0
CppOptions =
SccomVerbose = 0
[vopt]
; Turn on code coverage in vopt. Default is off.
; Coverage = sbceft
/src/grpSd/unitSdCardSynchronizer/src/SdCardSynchronizer-Rtl-ea.vhdl
71,3 → 71,4
oDataSync <= DataSync(gSyncCount - 1);
 
end architecture Rtl;
 
/src/grpMemory/unitSimpleDualPortedRam/src/SimpleDualPortedRam-Rtl-a.vhdl
9,7 → 9,7
 
architecture Rtl of SimpleDualPortedRam is
 
signal tempq : std_logic_vector(31 downto 0);
signal tempq : std_logic_vector(31 downto 0);
signal rdaddr, wraddr : unsigned(6 downto 0);
 
begin
17,12 → 17,12
Ram_inst: ENTITY work.CycSimpleDualPortedRam
PORT map
(
clock => iClk,
data => std_logic_vector(iDataRw),
clock => iClk,
data => std_logic_vector(iDataRw),
rdaddress => std_logic_vector(rdaddr),
wraddress => std_logic_vector(wraddr),
wren => iWeRW,
q => tempq
wren => iWeRW,
q => tempq
);
 
oDataR <= std_ulogic_vector(tempq);

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.