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  • This comparison shows the changes necessary to convert path 
    /sdhc-sc-core/trunk
    from Rev 164 to Rev 165
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  •

Rev 164 → Rev 165

/src/grpSd/unitSdWbSdControllerSync/src/SdWbSdControllerSync-Rtl-ea.vhdl
40,15 → 40,15
 
);
port (
iRstSync : in std_ulogic;
 
-- clocked by iWbClk
iWbClk : in std_ulogic;
iWbRstSync : in std_ulogic;
iSdWb : in aSdWbSlaveToSdController;
oSdWb : out aSdControllerToSdWbSlave;
 
-- clocked by iSdClk
iSdClk : in std_ulogic;
iSdRstSync : in std_ulogic;
iSdController : in aSdControllerToSdWbSlave;
oSdController : out aSdWbSlaveToSdController
 
73,7 → 73,7
gSyncCount => gSyncCount
)
port map (
iRstSync => iRstSync,
iRstSync => iWbRstSync,
iToClk => iWbClk,
iSignal => iSdController.ReqOperation,
oSync => ReqOperationSync
84,7 → 84,7
gSyncCount => gSyncCount
)
port map (
iRstSync => iRstSync,
iRstSync => iSdRstSync,
iToClk => iSdClk,
iSignal => iSdWb.AckOperation,
oSync => AckOperationSync
108,7 → 108,7
)
port map (
iClk => iWbClk,
iRstSync => iRstSync,
iRstSync => iWbRstSync,
iLine => ReqOperationSync,
iClearEdgeDetected => cInactivated,
oEdgeDetected => ReqOperationEdge
121,7 → 121,7
)
port map (
iClk => iSdClk,
iRstSync => iRstSync,
iRstSync => iSdRstSync,
iLine => AckOperationSync,
iClearEdgeDetected => cInactivated,
oEdgeDetected => AckOperationEdge
/src/grpSd/unitSdTop/src/SdTop-Rtl-ea.vhdl
40,8 → 40,8
);
port (
-- Wishbone interface
iWbClk : in std_ulogic;
iRstSync : in std_ulogic;
iWbClk : in std_ulogic;
iWbRstSync : in std_ulogic;
 
iCyc : in std_ulogic;
iLock : in std_ulogic;
60,8 → 60,7
 
-- Sd interface
iSdClk : in std_ulogic;
inResetAsync : in std_ulogic;
 
iSdRstSync : in std_ulogic;
-- SD Card
ioCmd : inout std_logic;
oSclk : out std_ulogic;
141,9 → 140,10
gUseSameClocks => gUseSameClocks
)
port map (
iRstSync => iRstSync,
iWbClk => iWbClk,
iWbRstSync => iWbRstSync,
iSdClk => iSdClk,
iSdRstSync => iSdRstSync,
iSdWb => iSdWbSync,
oSdWb => oSdWbSync,
iSdController => iSdControllerSync,
153,7 → 153,7
SdWbSlave_inst : entity work.SdWbSlave
port map (
iClk => iWbClk,
iRstSync => iRstSync,
iRstSync => iWbRstSync,
 
-- wishbone
iWbCtrl => iWbCtrl,
181,7 → 181,7
)
port map (
iClk => iSdClk,
inResetAsync => inResetAsync,
iRstSync => iSdRstSync,
oHighSpeed => HighSpeed,
iSdCmd => SdCmdToController,
oSdCmd => SdCmdFromController,
195,7 → 195,7
SdCmd_inst: entity work.SdCmd(Rtl)
port map (
iClk => iSdClk,
inResetAsync => inResetAsync,
iRstSync => iSdRstSync,
iStrobe => SdStrobe,
iFromController => SdCmdFromController,
oToController => SdCmdToController,
206,7 → 206,7
SdData_inst: entity work.SdData
port map (
iClk => iSdClk,
inResetAsync => inResetAsync,
iRstSync => iSdRstSync,
iStrobe => SdStrobe,
iSdDataFromController => SdDataFromController,
oSdDataToController => SdDataToController,
225,7 → 225,7
)
port map (
iClk => iSdClk,
iRstSync => iRstSync,
iRstSync => iSdRstSync,
iHighSpeed => HighSpeed,
iDisable => DisableSdClk,
oSdStrobe => SdStrobe,
237,7 → 237,7
port map (
 
iClk => iSdClk,
iRstSync => iRstSync,
iRstSync => iSdRstSync,
iStrobe => SdInStrobe,
iCmd => ioCmd,
iData => ioData,
/src/grpSd/unitSdCmd/src/SdCmd-Rtl-ea.vhdl
35,7 → 35,7
entity SdCmd is
port (
iClk : in std_ulogic; -- Clk, rising edge
inResetAsync : in std_ulogic; -- Reset, asynchronous active low
iRstSync : in std_ulogic; -- Reset, synchronous active high
 
iStrobe : in std_ulogic; -- Strobe to send data
 
80,7 → 80,7
Cmd => (Cmd => '0',
En => '0'));
 
type aCrcOut is record
type aCrcOut is record
Clear : std_ulogic;
DataIn : std_ulogic;
Data : std_ulogic;
103,19 → 103,19
oCmd <= O.Cmd;
 
-- State register
CmdStateReg : process (iClk, inResetAsync)
CmdStateReg : process (iClk)
begin
if inResetAsync = cInactivated then
R <= cDefaultRegSet;
O <= cDefaultOutputRegSet;
if iClk'event and iClk = cActivated then
if iRstSync = cActivated then
R <= cDefaultRegSet;
O <= cDefaultOutputRegSet;
else
 
elsif iClk'event and iClk = cActivated then
 
if (iStrobe = cActivated) then
R <= NextR;
O <= NextO;
if (iStrobe = cActivated) then
R <= NextR;
O <= NextO;
end if;
end if;
 
end if;
end process CmdStateReg;
 
300,8 → 300,8
gPolynom => crc7)
port map(
iClk => iClk,
inResetAsync => inResetAsync,
iClear => CrcOut.Clear,
iRstSync => iRstSync,
iClear => CrcOut.Clear,
iStrobe => iStrobe,
iDataIn => CrcOut.DataIn,
iData => CrcOut.Data,
/src/grpSd/unitSdData/src/SdData-Rtl-a.vhdl
64,13 → 64,11
DisableSdClk => cInactivated);
 
type aCrcOut is record
Clear : std_ulogic;
DataIn : std_ulogic;
Data : std_ulogic_vector(3 downto 0);
end record aCrcOut;
 
constant cDefaultCrcOut : aCrcOut := (
Clear => cInactivated,
DataIn => cInactivated,
Data => (others => '0'));
 
100,26 → 98,25
oDisableSdClk <= R.DisableSdClk;
 
 
Regs : process (iClk, inResetAsync)
Regs : process (iClk)
begin
-- asynchronous reset
if (inResetAsync = cnActivated) then
R <= cDefaultReg;
 
-- clock event
elsif (iClk'event and iClk = cActivated) then
if (iClk'event and iClk = cActivated) then
if (iRstSync = cActivated) then
R <= cDefaultReg;
else
-- synchronous enable
if (iStrobe = cActivated) then
R <= NextR;
end if;
 
-- synchronous enable
if (iStrobe = cActivated) then
R <= NextR;
-- rdreq and wrreq have to be exactly one clock cycle wide
R.ReadWriteFifo.rdreq <= NextR.ReadWriteFifo.rdreq and iStrobe;
R.WriteReadFifo.wrreq <= NextR.WriteReadFifo.wrreq and iStrobe;
 
-- Clock has to be disabled before the next strobe is generated
R.DisableSdClk <= NextR.DisableSdClk;
end if;
 
-- rdreq and wrreq have to be exactly one clock cycle wide
R.ReadWriteFifo.rdreq <= NextR.ReadWriteFifo.rdreq and iStrobe;
R.WriteReadFifo.wrreq <= NextR.WriteReadFifo.wrreq and iStrobe;
 
-- Clock has to be disabled before the next strobe is generated
R.DisableSdClk <= NextR.DisableSdClk;
end if;
end process Regs;
 
469,9 → 466,9
)
port map (
iClk => iClk,
inResetAsync => inResetAsync,
iRstSync => iRstSync,
iStrobe => iStrobe,
iClear => CrcOut.Clear,
iClear => cInactivated,
iDataIn => CrcDataIn(idx),
iData => CrcOut.Data(idx),
oIsCorrect => CrcIn.Correct(idx),
/src/grpSd/unitSdData/src/SdData-e.vhdl
36,7 → 36,7
port (
-- clock
iClk : in std_ulogic;
inResetAsync : in std_ulogic;
iRstSync : in std_ulogic;
iStrobe : in std_ulogic;
 
/src/grpSd/unitTbdSd/Files.tcl
57,7 → 57,7
 
set svunits {Sd TbdSd}
 
set sysvlogparams [list +incdir+../../unitSdCardModel/src+../src+../../unitSdWbSlave/src+../../../grpVerification/unitLogger/src/]
set sysvlogparams [list +incdir+../../unitSdCardModel/src+../src+../../unitSdWbSlave/src+../../../grpVerification/unitLogger/src/+../../../grpSdVerification/unitSdCoreTransactionBFM/src+../../../grpSdVerification/unitSdCoreTransactionSeqGen/src+../../../grpSdVerification/unitSdCoreTransferFunction/src+../../../grpSdVerification/unitSdCoreChecker/src+../../../grpSdVerification/unitSdCoreTransaction/src+../../pkgSdWb/src/]
 
#set tb
set top Testbed
/src/grpSd/unitTbdSd/src/TbdSd.sv
33,8 → 33,9
initial begin
SdBusTransToken token;
SdBFM SdBfm = new(SdBus);
SdCardModel card = new(SdBfm);
SdCardModel card = new();
assert(card.randomize());
card.bfm = SdBfm;
 
fork
begin // generator
/src/grpSd/unitTbdSd/src/TbdSd-Rtl-ea.vhdl
141,7 → 141,6
oRty => oRty,
 
iSdClk => iClk,
inResetAsync => inResetAsync,
ioCmd => ioCmd,
oSclk => oSclk,
ioData => ioData,
/src/grpSd/unitSdVerificationTestbench/src/SdVerificationTestbench.sv
59,7 → 59,7
 
module Testbed();
logic Clk = 0;
logic nResetAsync = 0;
logic RstSync = 1;
 
ISdBus CardInterface();
IWishboneBus IWbBus();
81,17 → 81,17
IWbBus.ERR_I,
IWbBus.RTY_I,
Clk,
nResetAsync,
RstSync,
CardInterface.Cmd,
CardInterface.SClk,
CardInterface.Data);
 
always #5 Clk <= ~Clk;
always #5 IWbBus.CLK_I <= ~IWbBus.CLK_I;
always #7 IWbBus.CLK_I <= ~IWbBus.CLK_I;
 
initial begin
#10 nResetAsync <= 1;
#10 IWbBus.RST_I <= 0;
#20 RstSync <= 0;
#28 IWbBus.RST_I <= 0;
end
 
Test tb(CardInterface, IWbBus);
/src/grpSd/unitSdController/src/SdController-Rtl-a.vhdl
103,12 → 103,14
oSdWbSlave <= R.ToSdWbSlave;
oHighSpeed <= R.HighSpeed;
 
Regs : process (iClk, inResetAsync)
Regs : process (iClk, iRstSync)
begin
if (inResetAsync = cnActivated) then
R <= cDefaultSdControllerReg;
elsif (iClk'event and iClk = cActivated) then
R <= NextR;
if (iClk'event and iClk = cActivated) then
if (iRstSync = cActivated) then
R <= cDefaultSdControllerReg;
else
R <= NextR;
end if;
end if;
end process Regs;
 
831,7 → 833,7
)
port map (
iClk => iClk,
inResetAsync => inResetAsync,
iRstSync => iRstSync,
iEnable => TimeoutEnable,
iDisable => TimeoutDisable,
iMax => TimeoutMax,
/src/grpSd/unitSdController/src/SdController-e.vhdl
41,7 → 41,7
);
port (
iClk : in std_ulogic; -- rising edge
inResetAsync : in std_ulogic;
iRstSync : in std_ulogic;
oHighSpeed : out std_ulogic;
 
-- SdCmd
/src/grpCrc/unitCrc/src/Crc-Rtl-ea.vhdl
43,9 → 43,9
);
port (
iClk : in std_ulogic;
inResetAsync : in std_ulogic; -- Asynchronous low active reset
iClear : in std_ulogic; -- Synchronous reset for the registers
iRstSync : in std_ulogic; -- Synchronous high active reset
iStrobe : in std_ulogic; -- Strobe, only shift when it is activated
iClear : in std_ulogic; -- Clear register
iDataIn : in std_ulogic; -- Signal that currently data is shifted in.
-- Otherwise the current remainder is shifted out.
iData : in std_ulogic; -- Data input
69,15 → 69,13
begin
 
-- shift registers
crc : process (iClk, inResetAsync) is
crc : process (iClk) is
variable input : std_ulogic;
begin
if (inResetAsync = '0') then
regs <= (others => '0');
elsif (rising_edge(iClk)) then
if (iClear = '1') then
if (rising_edge(iClk)) then
if (iRstSync = '1') then
regs <= (others => '0');
elsif (iClear = '0') then
else
if (iStrobe = '1') then
if (iDataIn = '1') then
-- calculate CRC
99,6 → 97,10
regs(idx) <= regs(idx-1);
end loop;
end if;
if (iClear = '1') then
regs <= (others => '0');
end if;
end if;
end if;
end if;
/src/grpStrobesClocks/unitCounter/src/Counter-Rtl-a.vhdl
39,29 → 39,31
 
begin
 
Regs : process (iClk, inResetAsync)
Regs : process (iClk)
begin
if (inResetAsync = cnActivated) then
R <= cDefaultReg;
elsif (iClk'event and iClk = cActivated) then
oStrobe <= cInactivated;
if (iClk'event and iClk = cActivated) then
if (iRstSync = cActivated) then
R <= cDefaultReg;
else
oStrobe <= cInactivated;
 
if (iDisable = cActivated) then
R.Enabled <= cInactivated;
R.Counter <= to_unsigned(0, R.Counter'length);
if (iDisable = cActivated) then
R.Enabled <= cInactivated;
R.Counter <= to_unsigned(0, R.Counter'length);
 
elsif (iEnable = cActivated or R.Enabled = cActivated) then
R.Enabled <= cActivated;
elsif (iEnable = cActivated or R.Enabled = cActivated) then
R.Enabled <= cActivated;
 
if (R.Counter = iMax) then
R.Counter <= to_unsigned(0, R.Counter'length);
oStrobe <= cActivated;
R.Enabled <= cInactivated;
if (R.Counter = iMax) then
R.Counter <= to_unsigned(0, R.Counter'length);
oStrobe <= cActivated;
R.Enabled <= cInactivated;
 
else
R.Counter <= R.Counter + 1;
else
R.Counter <= R.Counter + 1;
end if;
 
end if;
 
end if;
end if;
end process Regs;
/src/grpStrobesClocks/unitCounter/src/Counter-e.vhdl
35,7 → 35,7
);
port (
iClk : in std_ulogic;
inResetAsync : in std_ulogic;
iRstSync : in std_ulogic;
iEnable : in std_ulogic;
iDisable : in std_ulogic;
iMax : in unsigned(gBitWidth - 1 downto 0);
/src/grpStrobesClocks/unitTimeoutGenerator/src/TimeoutGenerator-Rtl-a.vhdl
34,32 → 34,31
 
begin
 
Regs : process (iClk, inResetAsync)
Regs : process (iClk)
begin
if (iClk'event and iClk = cActivated) then
if (iRstSync = cActivated) then
Counter <= (others => '0');
Enabled <= cInactivated;
oTimeout <= cInactivated;
else
oTimeout <= cInactivated; -- Default
 
if (inResetAsync = cnActivated) then
Counter <= (others => '0');
Enabled <= cInactivated;
oTimeout <= cInactivated;
if (iDisable = cActivated) then
Enabled <= cInactivated;
Counter <= (others => '0');
 
elsif (iClk'event and iClk = cActivated) then
oTimeout <= cInactivated; -- Default
if (iDisable = cActivated) then
Enabled <= cInactivated;
Counter <= (others => '0');
elsif (iEnable = cActivated or Enabled = cActivated) then
Counter <= Counter + 1;
Enabled <= cActivated;
 
elsif (iEnable = cActivated or Enabled = cActivated) then
Counter <= Counter + 1;
Enabled <= cActivated;
if (Counter >= cMax) then
Counter <= to_unsigned(0, cBitWidth);
Enabled <= cInactivated;
oTimeout <= cActivated;
if (Counter >= cMax) then
Counter <= to_unsigned(0, cBitWidth);
Enabled <= cInactivated;
oTimeout <= cActivated;
end if;
end if;
end if;
 
end if;
end process Regs;
 
/src/grpStrobesClocks/unitTimeoutGenerator/src/TimeoutGenerator-e.vhdl
38,7 → 38,7
 
port (
iClk : in std_ulogic;
inResetAsync : in std_ulogic;
iRstSync : in std_ulogic;
iEnable : in std_ulogic;
iDisable : in std_ulogic;
oTimeout : out std_ulogic

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