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Rev 20 → Rev 21

/src/grpWishbone/pkgWishbone/src/Wishbone-p.vhdl
10,7 → 10,7
use ieee.std_logic_1164.all;
 
package Wishbone is
type endianness is (big, little);
type aEndian is (big, little);
 
subtype aCti is std_ulogic_vector(2 downto 0);
 
28,6 → 28,29
 
type aWbState is (idle);
 
-- Control inputs for a wishbone slave
-- Unfortunately unconstrained types in records are only supported in
-- VHDL2008, therefore signals with a range dependend on generics can not be
-- put inside the record (iSel, iAdr, iDat).
type aWbSlaveCtrlInput is record
-- Control signals
iCyc : std_ulogic; -- Indicates a bus cycle
iLock : std_ulogic; -- Indicates that the current cycle is not interruptable
iStb : std_ulogic; -- Indicates the selection of the slave
iWe : std_ulogic; -- Write enable, indicates whether the cycle is a read or write cycle
iCti : aCti; -- used for synchronous cycle termination
iBte : aBte; -- Burst type extension
end record;
 
-- Control output signals of a wishbone slave
-- See aWbSlaveCtrlInput for a explanation why oDat is not in the record.
type aWbSlaveCtrlOutput is record
-- Control signals
oAck : std_ulogic; -- Indicates the end of a normal bus cycle
oErr : std_ulogic; -- Indicates an error
oRty : std_ulogic; -- Indicates that the request should be retried
end record;
 
end package Wishbone;
 
 
/src/grpWishbone/unitWbSlave/src/WbSlave-Rtl-ea.vhdl
14,51 → 14,46
 
entity WbSlave is
generic (
gPortSize : natural := 8; -- in bits, only 8, 16, 32 and 64 are valid
gPortGranularity : natural := 8; -- in bits, only 8, 16, 32 and 64 are valid
gMaximumOperandSize : natural := 8; -- in bits, only 8, 16, 32 and 64 are valid
gEndian : endianness := big -- if the port size equals the granularity
gPortSize : natural := 8; -- in bits, only 8, 16, 32 and 64 are valid
gPortGranularity : natural := 8; -- in bits, only 8, 16, 32 and 64 are valid
gMaximumOperandSize : natural := 8; -- in bits, only 8, 16, 32 and 64 are valid
gEndian : aEndian := little -- if the port size equals the granularity
-- this setting does not make a difference
);
port (
-- Control
iClk : in std_ulogic; -- Clock, rising clock edge
iRstSync : in std_ulogic; -- Reset, active high, synchronous
 
iCyc : in std_ulogic; -- Indicates a bus cycle
iLock : in std_ulogic; -- Indicates that the current cycle is not interruptable
iSel : in std_ulogic_vector(gPortSize/gPortGranularity - 1 downto 0); -- TODO Check this
iStb : in std_ulogic; -- Indicates the selection of the slave
iWe : in std_ulogic; -- Write enable, indicates whether the cycle is a read or write cycle
oAck : out std_ulogic; -- Indicates the end of a normal bus cycle
oErr : out std_ulogic; -- Indicates an error
oRty : out std_ulogic; -- Indicates that the request should be retried
iWbSlave : in aWbSlaveCtrlInput; -- All control signals for a wishbone slave
oWbSlave : out aWbSlaveCtrlOutput; -- All output signals for a wishbone slave
 
iCti : in aCti := "000"; -- used for synchronous cycle termination
iBte : in aBte; -- Burst type extension
 
-- Data
-- Data signals
iSel : in std_ulogic_vector(gPortSize/gPortGranularity - 1 downto 0);
-- Selects which parts of iDat are valid
iAdr : in std_ulogic_vector(gPortSize-1 downto integer(log2(
real(gPortGranularity) )) - 1); -- address
real(gPortGranularity) )) - 1); -- Address
iDat : in std_ulogic_vector(gPortSize-1 downto 0); -- Input data, see iSel
 
iDat : in std_ulogic_vector(gPortSize-1 downto 0); -- Data input
oDat : out std_ulogic_vector(gPortSize-1 downto 0) -- Data output
 
-- Tags are currently not supported
oDat : out std_ulogic_vector(gPortSize-1 downto 0) -- Output data, see iSel
);
 
begin
 
-- check valid config with assertions
assert (gPortSize = 8 or gPortSize = 16 or gPortSize = 32 or gPortSize =
64) report "gPortSize is invalid." severity failure;
64) report "gPortSize is invalid, valid values are 8,16,32 and 64." severity failure;
 
assert (gPortGranularity = 8 or gPortGranularity = 16 or
gPortGranularity = 32 or gPortGranularity = 64) report "gPortGranularity is invalid." severity failure;
gPortGranularity = 32 or gPortGranularity = 64) report
"gPortGranularity is invalid, valid values are 8,16,32 and 64." severity failure;
 
assert (gMaximumOperandSize = 8 or gMaximumOperandSize = 16 or
gMaximumOperandSize = 32 or gMaximumOperandSize = 64) report
"gMaximumOperandSize is invalid." severity failure;
"gMaximumOperandSize is invalid, valid values are 8,16,32 and 64." severity failure;
 
assert (gPortGranularity <= gPortSize) report
"gPortGranularity is bigger than gPortSize" severity failure;
end entity;
 
architecture Rtl of WbSlave is

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