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https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk
Subversion Repositories sdhc-sc-core
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- This comparison shows the changes necessary to convert path
/sdhc-sc-core/trunk
- from Rev 21 to Rev 22
- ↔ Reverse comparison
Rev 21 → Rev 22
/src/grpWishbone/pkgWishbone/src/Wishbone-p.vhdl
26,8 → 26,6
constant cBteEightBeat : aBte := "10"; |
constant cBteSixteenBeat : aBte := "11"; |
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type aWbState is (idle); |
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-- Control inputs for a wishbone slave |
-- Unfortunately unconstrained types in records are only supported in |
-- VHDL2008, therefore signals with a range dependend on generics can not be |
34,12 → 32,12
-- put inside the record (iSel, iAdr, iDat). |
type aWbSlaveCtrlInput is record |
-- Control signals |
iCyc : std_ulogic; -- Indicates a bus cycle |
iLock : std_ulogic; -- Indicates that the current cycle is not interruptable |
iStb : std_ulogic; -- Indicates the selection of the slave |
iWe : std_ulogic; -- Write enable, indicates whether the cycle is a read or write cycle |
iCti : aCti; -- used for synchronous cycle termination |
iBte : aBte; -- Burst type extension |
Cyc : std_ulogic; -- Indicates a bus cycle |
Lock : std_ulogic; -- Indicates that the current cycle is not interruptable |
Stb : std_ulogic; -- Indicates the selection of the slave |
We : std_ulogic; -- Write enable, indicates whether the cycle is a read or write cycle |
Cti : aCti; -- used for synchronous cycle termination |
Bte : aBte; -- Burst type extension |
end record; |
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-- Control output signals of a wishbone slave |
46,11 → 44,15
-- See aWbSlaveCtrlInput for a explanation why oDat is not in the record. |
type aWbSlaveCtrlOutput is record |
-- Control signals |
oAck : std_ulogic; -- Indicates the end of a normal bus cycle |
oErr : std_ulogic; -- Indicates an error |
oRty : std_ulogic; -- Indicates that the request should be retried |
Ack : std_ulogic; -- Indicates the end of a normal bus cycle |
Err : std_ulogic; -- Indicates an error |
Rty : std_ulogic; -- Indicates that the request should be retried |
end record; |
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constant cDefaultWbSlaveCtrlOutput : aWbSlaveCtrlOutput := ('0','0','0'); |
constant cActivated : std_ulogic := '1'; |
constant cInactivated : std_ulogic := '0'; |
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end package Wishbone; |
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/src/grpWishbone/unitWbSlave/src/WbSlave-Rtl-ea.vhdl
58,7 → 58,29
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architecture Rtl of WbSlave is |
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type aWbState is (idle); |
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signal State, NextState : aWbState := idle; |
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begin |
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WbStateReg : process (iClk, iRstSync) |
begin |
if (iClk'event and iClk = cActivated) then |
if (iRstSync = cActivated) then -- sync. reset |
State <= idle; |
else |
State <= NextState; |
end if; |
end if; |
end process WbStateReg ; |
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WbNextStateAndOutputs : process (iWbSlave, iSel, iDat, iAdr) |
begin |
-- Default Assignments |
oDat <= (others => cInactivated); |
oWbSlave <= cDefaultWbSlaveCtrlOutput; |
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end process WbNextStateAndOutputs; |
end architecture Rtl; |
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