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    /sdhc-sc-core/trunk
    from Rev 24 to Rev 25
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Rev 24 → Rev 25

/src/grpWishbone/unitWbSlave/src/WbSlave-Rtl-ea.vhdl
59,10 → 59,13
 
architecture Rtl of WbSlave is
 
type aWbState is (idle);
type aWbState is (idle, ClassicRead, ClassicWrite);
 
signal State, NextState : aWbState := idle;
 
constant cValid : std_ulogic_vector(gPortSize - 1 downto 0) := (others =>
'1');
 
begin
WbStateReg : process (iClk, iRstSync)
81,7 → 84,46
-- Default Assignments
oDat <= (others => cInactivated);
oWbSlave <= cDefaultWbSlaveCtrlOutput;
NextState <= State;
 
-- Determine next state
case State is
when idle =>
if iWbSlave.Cyc = cActivated and iWbSlave.Stb = cActivated then
case iWbSlave.Cti is
when cCtiClassicCycle =>
if (iWbSlave.We = cInactivated) then
NextState <= ClassicRead;
elsif (iWbSlave.We = cActivated) then
NextState <= ClassicWrite;
end if;
when others => null;
end case;
end if;
 
when ClassicRead =>
assert (iWbSlave.Cyc = cActivated) report
"Cyc deactivated mid cyclus" severity warning;
 
oWbSlave.Ack <= cActivated;
oDat <= cValid; -- TODO: Read real data, use Sel
NextState <= idle;
 
when ClassicWrite =>
assert (iWbSlave.Cyc = cActivated) report
"Cyc deactivated mid cyclus" severity warning;
 
oWbSlave.Ack <= cActivated;
-- TODO: Save data, use Sel
NextState <= idle;
 
when others => null;
end case;
 
end process WbNextStateAndOutputs;
end architecture Rtl;
 
/src/grpWishbone/unitWbSlave/src/tbWbSlave-Bhv-ea.vhdl
0,0 → 1,54
-------------------------------------------------
-- file: tbWbSlave-Bhv-ea.vhdl
-- author: Rainer Kastl
--
-- Testbench for wishbone slave (WbSlave-Rtl-ea.vhdl)
-------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
--use ieee.math_real.all;
use work.Global.all;
use work.wishbone.all;
 
entity tbWbSlave is
generic (gClkPeriod : time := 10 ns);
end entity;
 
architecture Bhv of tbWbSlave is
 
signal Clk, RstSync : std_ulogic := cInactivated;
signal iWbSlave : aWbSlaveCtrlInput;
signal oWbSlave : aWbSlaveCtrlOutput;
signal Sel : std_ulogic_vector(0 downto 0);
signal Adr : std_ulogic_vector(7 downto 2);
signal DataToSlave, DataFromSlave : std_ulogic_vector(7 downto 0);
 
begin
 
-- Clock generator
Clk <= not Clk after gClkPeriod/2;
RstSync <= cActivated after 2*gClkPeriod,
cInactivated after 3*gClkPeriod;
 
Stimulus : process
begin
wait;
end process Stimulus ;
duv : entity work.WbSlave(Rtl)
generic map (gPortSize => 8,
gPortGranularity => 8,
gMaximumOperandSize => 8,
gEndian => little)
port map(iClk => Clk,
iRstSync => RstSync,
iWbSlave => iWbSlave,
oWbSlave => oWbSlave,
iSel => Sel,
iAdr => Adr,
iDat => DataToSlave,
oDat => DataFromSlave);
 
end architecture Bhv;
 
/src/grpWishbone/unitWbSlave/sim/tbwb.tcl
1,8 → 1,8
set pkgs {Global Global
Wishbone Wishbone}
set units {Wishbone WbSlave {Rtl}}
set tb Crc
set tbarch bhv
set tb WbSlave
set tbarch Bhv
 
vlib work
vmap work work
15,9 → 15,9
vcom ../../../grp$grp/unit$en/src/$en-$arch-ea.vhdl
}
 
#vcom ../../unit$tb/src/tb$tb-$tbarch-ea.vhdl
vcom ../../unit$tb/src/tb$tb-$tbarch-ea.vhdl
 
#vsim tb$tb
vsim tb$tb
 
#do wave.do
#run -all
do wave.do
run -all

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