URL
https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk
Subversion Repositories sdhc-sc-core
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- This comparison shows the changes necessary to convert path
/sdhc-sc-core/trunk
- from Rev 27 to Rev 28
- ↔ Reverse comparison
Rev 27 → Rev 28
/src/grpWishbone/unitWbSlave/src/tbWbSlave-Bhv-ea.vhdl
16,18 → 16,19
end entity; |
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architecture Bhv of tbWbSlave is |
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subtype aAdr is std_ulogic_vector(7 downto 2); |
subtype aData is std_ulogic_vector(7 downto 0); |
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signal Clk, RstSync : std_ulogic := cInactivated; |
signal iWbSlave : aWbSlaveCtrlInput; |
signal oWbSlave : aWbSlaveCtrlOutput; |
signal Sel : std_ulogic_vector(0 downto 0); |
signal Adr : std_ulogic_vector(7 downto 2); |
signal DataToSlave, DataFromSlave : std_ulogic_vector(7 downto 0); |
signal Adr : aAdr; |
signal DataToSlave, DataFromSlave : aData; |
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signal Finished : std_ulogic := cInactivated; |
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constant cValid : std_ulogic_vector(7 downto 0) := (others => |
'1'); |
constant cValid : std_ulogic_vector(7 downto 0) := (others => '1'); |
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begin |
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37,27 → 38,52
cInactivated after 3*gClkPeriod; |
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Stimulus : process |
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procedure readData (constant address: in aAdr; variable data : out aData) is |
begin |
iWbSlave.Cyc <= cActivated; |
iWbSlave.Stb <= cActivated; |
iWbSlave.We <= cInactivated; |
iWbSlave.Cti <= cCtiClassicCycle; |
Adr <= address; |
Sel <= "1"; |
wait until Clk = cActivated; |
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wait until Clk = cActivated and oWbSlave.Ack = cActivated; |
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assert (oWbSlave.Ack = cActivated) report |
"Read not acknowledged. Waitstate?" severity error; |
assert (DataFromSlave = cValid) report |
"Invalid data after read" severity error; |
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data := DataFromSlave; |
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end procedure readData; |
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procedure writeData (constant address: in aAdr; constant data: in aData) is |
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begin |
iWbSlave.Cyc <= cActivated; |
iWbSlave.Stb <= cActivated; |
iWbSlave.We <= cInactivated; |
iWbSlave.Cti <= cCtiClassicCycle; |
Adr <= address; |
Sel <= "1"; |
DataToSlave <= data; |
wait until Clk = cActivated; |
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wait until Clk = cActivated and oWbSlave.Ack = cActivated; |
end procedure writeData; |
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variable tempData : aData; |
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begin |
wait for 6*gClkPeriod; |
-- Classic Reads |
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writeData("000001", X"A0"); |
readData("000001", tempData); |
wait until Clk = cActivated; |
iWbSlave.Cyc <= cActivated; |
iWbSlave.Stb <= cActivated; |
iWbSlave.We <= cInactivated; |
iWbSlave.Cti <= cCtiClassicCycle; |
Adr <= "000001"; |
Sel <= "1"; |
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wait until Clk = cActivated; |
wait until Clk = cActivated; |
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assert (oWbSlave.Ack = cActivated) report |
"Read not acknowledged. Waitstate?" severity error; |
assert (DataFromSlave = cValid) report |
"Invalid data after read" severity error; |
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wait until Clk = cActivated; |
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Finished <= cActivated; |
wait; |
end process Stimulus; |