URL
https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk
Subversion Repositories sdhc-sc-core
Compare Revisions
- This comparison shows the changes necessary to convert path
/sdhc-sc-core/trunk
- from Rev 34 to Rev 35
- ↔ Reverse comparison
Rev 34 → Rev 35
/src/grpSd/unitSdCmd/src/SdCmd-Rtl-ea.vhdl
20,7 → 20,7
inResetAsync : in std_ulogic; -- Reset, asynchronous active low |
|
iCmdContent: in aSdCmdContent; -- Content to send to card |
ioCmd : inout std_ulogic -- Cmd line to and from card |
ioCmd : inout std_logic -- Cmd line to and from card |
); |
end entity SdCmd; |
|
38,15 → 38,16
CmdStateReg : process (iClk, inResetAsync) |
begin |
if inResetAsync = cInactivated then |
State <= endbit; |
State <= idle; |
Counter <= to_unsigned(0, Counter'length); |
elsif iClk'event and iClk = cActivated then |
State <= NextState; |
Counter <= NextCounter; |
end if; |
end process CmdStateReg; |
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-- Comb. process |
NextStateAndOutput : process (iCmdContent, State) |
NextStateAndOutput : process (iCmdContent, State, Counter) |
|
procedure NextStateWhenAllSent (constant length : in natural; constant toState : in aSdCmdState) is |
begin |
81,24 → 82,47
when idle => |
-- todo: implement Sync. with host |
NextState <= startbit; |
CrcDataIn <= cActivated; |
CrcData <= cSdStartBit; |
|
when startbit => |
ioCmd <= cSdStartBit; |
NextState <= transbit; |
CrcDataIn <= cActivated; |
CrcData <= cSdTransBitHost; |
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when transbit => |
ioCmd <= cSdTransBitHost; |
NextState <= cmdid; |
CrcDataIn <= cActivated; |
CrcData <= iCmdContent.id(to_integer(NextCounter)); |
|
when cmdid => |
SendBitsAndCalcCrc(iCmdContent.id, arg); |
-- SendBitsAndCalcCrc(iCmdContent.id, arg); |
ioCmd <= iCmdContent.id(to_integer(NextCounter)); |
if (NextCounter < iCmdContent.id'length-2) then |
CrcData <= iCmdContent.id(to_integer(NextCounter)+1); |
else |
CrcData <= iCmdContent.arg(0); |
end if; |
CrcDataIn <= cActivated; |
NextStateWhenAllSent(iCmdContent.id'length, arg); |
|
|
when arg => |
SendBitsAndCalcCrc(iCmdContent.arg, crc); |
-- SendBitsAndCalcCrc(iCmdContent.arg, crc); |
ioCmd <= iCmdContent.arg(to_integer(NextCounter)); |
if (NextCounter < iCmdContent.arg'length-2) then |
CrcData <= iCmdContent.arg(to_integer(NextCounter)+1); |
CrcDataIn <= cActivated; |
else |
CrcDataIn <= cInactivated; |
end if; |
NextStateWhenAllSent(iCmdContent.arg'length, crc); |
|
when crc => |
ioCmd <= SerialCrc; |
NextStateWhenAllSent(crc7'length, endbit); |
NextStateWhenAllSent(crc7'length-1, endbit); |
|
when endbit => |
ioCmd <= cSdEndBit; |
/src/grpSd/unitSdCmd/src/tbSdCmd-Bhv-ea.vhdl
2,5 → 2,73
-- file: tbSdCmd-Bhv-ea.vhdl |
-- author: Rainer Kastl |
-- |
-- |
-- Simple testbench for the SDCmd entity |
------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
use work.Global.all; |
use work.Sd.all; |
|
entity tbSdCmd is |
generic (gClkPeriod : time := 10 ns); |
end entity tbSdCmd; |
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architecture Bhv of tbSdCmd is |
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signal Clk : std_ulogic := cInactivated; |
signal Finished : std_ulogic := cInactivated; |
signal nResetAsync : std_ulogic; |
signal CmdContent : aSdCmdContent; |
signal Cmd : std_ulogic; |
|
signal sentCmd : std_ulogic_vector(47 downto 0) := (others => 'U'); |
signal counter : integer := 0; |
signal save : std_ulogic := cInactivated; |
|
|
begin |
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-- Clock generator |
Clk <= not Clk after gClkPeriod/2 when (Finished = cInactivated); |
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-- Reset |
nResetAsync <= cnActivated after 2*gClkPeriod, |
cnInactivated after 3*gClkPeriod; |
|
Finished <= cActivated after 53*gClkPeriod; |
|
save <= cActivated after 36 ns; |
SaveCmd : process (Clk, save) |
begin |
if (Clk'event and Clk = cActivated and save = cActivated) then |
if (counter < sentCmd'length) then |
sentCmd(sentCmd'length - 1 - counter) <= Cmd; |
counter <= counter + 1; |
end if; |
end if; |
end process SaveCmd ; |
|
-- Stimuli: |
-- Cmd <= 'L'; |
CmdContent.id <= cSdCmdGoIdleState; |
CmdContent.arg <= (others => '0'); |
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Stimuli : process is |
begin |
wait for 54*gClkPeriod; |
assert(sentCmd = "010000000000000000000000000000000000000010010101") report |
"sentCmd invalid: " & integer'image(to_integer(unsigned(sentCmd))) severity error; |
wait; |
end process Stimuli; |
|
DUT: entity work.SdCmd(Rtl) |
port map( |
iClk => Clk, |
inResetAsync => nResetAsync, |
iCmdContent => CmdContent, |
ioCmd => Cmd |
); |
|
end architecture Bhv; |
/src/grpSd/unitSdCmd/sim/tbSdCmd.tcl
17,9 → 17,9
vcom ../../../grp$grp/unit$en/src/$en-$arch-ea.vhdl |
} |
|
#vcom ../../unit$tb/src/tb$tb-$tbarch-ea.vhdl |
vcom ../../unit$tb/src/tb$tb-$tbarch-ea.vhdl |
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#vsim tb$tb |
vsim tb$tb |
|
#do wave.do |
#run -all |
do wave.do |
run -all |
/src/grpSd/unitSdCmd/sim/wave.do
0,0 → 1,46
onerror {resume} |
quietly WaveActivateNextPane {} 0 |
add wave -noupdate -format Logic /tbsdcmd/clk |
add wave -noupdate -format Logic /tbsdcmd/finished |
add wave -noupdate -format Logic /tbsdcmd/nresetasync |
add wave -noupdate -format Literal /tbsdcmd/cmdcontent |
add wave -noupdate -format Logic /tbsdcmd/cmd |
add wave -noupdate -format Literal /tbsdcmd/sentcmd |
add wave -noupdate -format Literal /tbsdcmd/counter |
add wave -noupdate -format Logic /tbsdcmd/dut/iocmd |
add wave -noupdate -format Literal /tbsdcmd/dut/state |
add wave -noupdate -format Literal /tbsdcmd/dut/nextstate |
add wave -noupdate -format Logic /tbsdcmd/dut/crcclear |
add wave -noupdate -format Logic /tbsdcmd/dut/crcdatain |
add wave -noupdate -format Logic /tbsdcmd/dut/crcdata |
add wave -noupdate -format Logic /tbsdcmd/dut/serialcrc |
add wave -noupdate -format Literal /tbsdcmd/dut/counter |
add wave -noupdate -format Literal /tbsdcmd/dut/nextcounter |
add wave -noupdate -format Literal /tbsdcmd/dut/icmdcontent |
add wave -noupdate -format Logic /tbsdcmd/dut/inresetasync |
add wave -noupdate -format Logic /tbsdcmd/dut/iclk |
add wave -noupdate -format Logic /tbsdcmd/dut/crc7_inst/iclk |
add wave -noupdate -format Logic /tbsdcmd/dut/crc7_inst/inresetasync |
add wave -noupdate -format Logic /tbsdcmd/dut/crc7_inst/iclear |
add wave -noupdate -format Logic /tbsdcmd/dut/crc7_inst/idatain |
add wave -noupdate -format Logic /tbsdcmd/dut/crc7_inst/idata |
add wave -noupdate -format Logic /tbsdcmd/dut/crc7_inst/oserial |
add wave -noupdate -format Literal /tbsdcmd/dut/crc7_inst/oparallel |
add wave -noupdate -format Literal /tbsdcmd/dut/crc7_inst/regs |
TreeUpdate [SetDefaultTree] |
WaveRestoreCursors {{Cursor 1} {194 ns} 0} |
configure wave -namecolwidth 150 |
configure wave -valuecolwidth 100 |
configure wave -justifyvalue left |
configure wave -signalnamewidth 1 |
configure wave -snapdistance 10 |
configure wave -datasetprefix 0 |
configure wave -rowmargin 4 |
configure wave -childrowmargin 2 |
configure wave -gridoffset 0 |
configure wave -gridperiod 1 |
configure wave -griddelta 40 |
configure wave -timeline 0 |
configure wave -timelineunits ns |
update |
WaveRestoreZoom {0 ns} {567 ns} |
/src/grpGlobal/pkgGlobal/src/Global-p.vhdl
13,6 → 13,8
|
constant cActivated : std_ulogic := '1'; |
constant cInactivated : std_ulogic := '0'; |
constant cnActivated : std_ulogic := '0'; |
constant cnInactivated : std_ulogic := '1'; |
|
end package Global; |
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