OpenCores
URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /sdhc-sc-core/trunk
    from Rev 85 to Rev 86
    ↔ Reverse comparison
  •

Rev 85 → Rev 86

/src/grpSd/unitSdController/src/SdController-Rtl-ea.vhdl
30,7 → 30,7
 
type aSdControllerState is (startup, init, idle, invalidCard);
type aCmdRegion is (CMD0, CMD8, CMD55, ACMD41, CMD2, CMD3);
type aRegion is (send, receive);
type aRegion is (send, receive, waitstate);
constant cDefaultoSdCmd : aSdCmdFromController := (
(id => (others => '0'),
100,10 → 100,10
oSdCmd.Valid <= cActivated;
 
if (iSdCmd.Ack = cActivated) then
NextR.Region <= receive;
NextR.Region <= waitstate;
end if;
 
when receive =>
when waitstate =>
TimeoutEnable <= cActivated;
 
if (Timeout = cActivated) then
128,27 → 128,39
 
when receive =>
oLedBank(0) <= cActivated;
TimeoutEnable <= cActivated;
 
if (iSdCmd.Valid = cActivated) then
if (iSdCmd.Content.id = cSdCmdSendIfCond and iSdCmd.Content.arg = cSdArgVoltage) then
NextR.HCS <= cActivated;
NextR.CmdRegion <= CMD55;
NextR.Region <= send;
NextR.Region <= waitstate;
NextR.HCS <= cActivated;
 
else
NextR.State <= invalidCard;
end if;
-- elsif timeout
elsif (Timeout = cActivated) then
NextR.HCS <= cInactivated;
NextR.CmdRegion <= CMD55;
NextR.Region <= send;
end if;
 
when waitstate =>
TimeoutEnable <= cActivated;
 
if (Timeout = cActivated) then
NextR.CmdRegion <= CMD55;
NextR.Region <= send;
end if;
 
when others =>
report "SdController: Unhandled state" severity error;
end case;
 
when CMD55 =>
oLedBank(1) <= cActivated;
 
case R.Region is
when send =>
oLedBank(1) <= cActivated;
oSdCmd.Content.id <= cSdNextIsACMD;
oSdCmd.Content.arg <= cSdACMDArg;
oSdCmd.Valid <= cActivated;
158,7 → 170,6
end if;
 
when receive =>
oLedBank(1) <= cActivated;
oLedBank(0) <= cActivated;
 
if (iSdCmd.Valid = cActivated) then
166,8 → 177,7
NextR.CmdRegion <= CMD55;
 
if (iSdCmd.Content.arg(cSdArgAppCmdPos) = cActivated) then
NextR.CmdRegion <= ACMD41;
NextR.Region <= send;
NextR.Region <= waitstate;
end if;
else
NextR.State <= invalidCard;
175,6 → 185,14
-- elsif timeout
end if;
 
when waitstate =>
TimeoutEnable <= cActivated;
 
if (Timeout = cActivated) then
NextR.CmdRegion <= ACMD41;
NextR.Region <= send;
end if;
 
when others =>
report "SdController: Unhandled state" severity error;
end case;
196,7 → 214,8
end if;
 
when receive =>
oLedBank(0) <= cActivated;
oLedBank(0) <= cActivated;
TimeoutEnable <= cActivated;
 
if (iSdCmd.Valid = cActivated) then
NextR.CmdRegion <= CMD55;
215,7 → 234,9
end if;
end if;
end if;
-- elsif timeout
elsif (Timeout = cActivated) then
NextR.CmdRegion <= CMD55;
NextR.Region <= send;
end if;
 
when others =>
/src/grpRs232/unitRs232Tx/Files.tcl
0,0 → 1,8
set pkgs {Global Global
Rs232 Rs232}
set units {Rs232 Rs232Tx {Rtl}}
 
set tbunits {StrobesClocks StrobeGen Rtl}
 
set tb {Rs232 Rs232Tx Bhv}
 
/src/grpRs232/unitRs232Tx/src/tbRs232Tx-Bhv-ea.vhdl
0,0 → 1,107
--
-- Title: Testbench for Rs232Tx
-- File: tbRs232Tx-Bhv-ea.vhdl
-- Author: Copyright 2010: Rainer Kastl
-- Standard: VHDL'93
--
-- Description:
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Global.all;
use work.Rs232.all;
 
entity tbRs232Tx is
end entity tbRs232Tx;
 
architecture Bhv of tbRs232Tx is
 
constant cClkFrequency : natural := 25E6;
constant cBaudRate : natural := 9600;
constant cResetTime : time := 1 sec / cClkFrequency * 3;
 
signal Clk : std_ulogic := cActivated;
signal nResetAsync : std_ulogic := cnActivated;
signal iRs232Tx : aiRs232Tx;
signal oRs232Tx : aoRs232Tx;
signal Finished : std_ulogic := cInactivated;
 
begin
 
Clk <= not Clk after 1 sec / cClkFrequency / 2 when Finished = cInactivated;
nResetAsync <= cnInactivated after cResetTime;
 
Stimuli : process is
begin
iRs232Tx.Transmit <= cActivated;
iRs232Tx.Data <= (others => '-');
iRs232Tx.DataAvailable <= cInactivated;
 
wait for cResetTime;
 
wait for 1 us;
 
iRs232Tx.Data <= X"5A";
iRs232Tx.DataAvailable <= cActivated;
 
wait until (Clk = cActivated and oRs232Tx.DataWasRead = cActivated);
 
iRs232Tx.DataAvailable <= cInactivated;
 
wait until Clk = cActivated;
wait until Clk = cActivated;
iRs232Tx.Data <= X"7E";
iRs232Tx.DataAvailable <= cActivated;
 
wait until (Clk = cActivated and oRs232Tx.DataWasRead = cActivated);
 
iRs232Tx.Data <= X"96";
 
wait until Clk = cActivated;
 
wait until (Clk = cActivated and oRs232Tx.DataWasRead = cActivated);
 
iRs232Tx.DataAvailable <= cInactivated;
 
wait for 500 us;
 
iRs232Tx.Data <= X"97";
iRs232Tx.DataAvailable <= cActivated;
 
wait until (Clk = cActivated and oRs232Tx.DataWasRead = cActivated);
 
iRs232Tx.DataAvailable <= cInactivated;
iRs232Tx.Transmit <= cInactivated;
 
wait for 5 ms;
 
Finished <= cActivated;
 
wait;
end process Stimuli;
 
StrobeGen_Rs232 : entity work.StrobeGen
generic map (
gClkFrequency => cClkFrequency,
gStrobeCycleTime => 1 sec / cBaudRate)
port map (
iClk => Clk,
inResetAsync => nResetAsync,
oStrobe => iRs232Tx.BitStrobe);
 
DUT: entity work.Rs232Tx
generic map (
gDataBitWidth => 8
)
port map (
iClk => Clk,
inResetAsync => nResetAsync,
iRs232Tx => iRs232Tx,
oRs232Tx => oRs232Tx
);
 
end architecture Bhv;
 
/src/grpRs232/unitRs232Tx/sim/Rs232Tx-unattended.tcl
0,0 → 1,3
set script Rs232Tx.tcl
 
do "../../../sim/unattended.tcl"
/src/grpRs232/unitRs232Tx/sim/Rs232Tx.tcl
0,0 → 1,3
source ../Files.tcl
source ../../../sim/sim.tcl
 
/src/grpRs232/unitRs232Tx/sim/Makefile
0,0 → 1,9
# Makefile for simulating wishbone slaves
 
include ../../../../Makefile.rules
 
all: Rs232Tx-unattended.sim
 
clean:
rm -rf vsim.wlf work
 
/src/sim/sim.tcl
46,6 → 46,12
}
}
 
if [info exists tbunits] {
foreach {grp en arch} $tbunits {
compileUnit $grp $en $arch
}
}
 
if [info exists tb] {
foreach {grp en arch} $tb {
compileTb $grp $en $arch
/Makefile
1,6 → 1,6
# Recursive makefile for simulations
 
SIMS = grpCrc/unitCrc grpWishbone/unitWbSlave grpSd/unitSdCmd grpSd/unitSdCardModel grpStrobesClocks/unitTimeoutGenerator
SIMS = grpCrc/unitCrc grpWishbone/unitWbSlave grpSd/unitSdCmd grpSd/unitSdCardModel grpStrobesClocks/unitTimeoutGenerator grpRs232/unitRs232Tx
SYSVSIMS = grpSd/unitSdVerificationTestbench
SYNS = grpCrc/unitCrc grpSd/unitSdCmd grpSd/unitSdTop grpSd/unitTbdSd
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.