URL
https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk
Subversion Repositories sdhc-sc-core
Compare Revisions
- This comparison shows the changes necessary to convert path
/sdhc-sc-core/trunk
- from Rev 91 to Rev 92
- ↔ Reverse comparison
Rev 91 → Rev 92
/src/grpSd/unitSdData/Files.tcl
0,0 → 1,9
set pkgs {Global Global |
Sd Sd |
Crc CRCs} |
|
set units {Crc Crc {Rtl} |
Sd SdData {Rtl}} |
|
set tb {Sd SdData Bhv} |
|
/src/grpSd/unitSdData/src/tbSdData-Bhv-ea.vhdl
0,0 → 1,82
-- |
-- Title: Testbench for SdData |
-- File: tbSdData-Bhv-ea.vhdl |
-- Author: Copyright 2010: Rainer Kastl |
-- Standard: VHDL'93 |
-- |
-- Description: |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
use work.Global.all; |
use work.Sd.all; |
|
entity tbSdData is |
end entity tbSdData; |
|
architecture Bhv of tbSdData is |
|
constant cClkFrequency : natural := 25E6; |
constant cClkPeriod : time := 1 sec / cClkFrequency / 2; |
constant cResetTime : time := 4 * cClkPeriod; |
|
signal Clk : std_ulogic := cActivated; |
signal nResetAsync : std_ulogic := cnActivated; |
signal Finished : std_ulogic := cInactivated; |
|
signal FromController : aSdDataFromController; |
signal ToController : aSdDataToController; |
|
signal Data : std_logic_vector(3 downto 0); |
|
begin |
|
Clk <= not Clk after cClkPeriod when Finished = cInactivated; |
nResetAsync <= cnInactivated after cResetTime; |
|
Stimuli : process |
begin |
FromController.Valid <= cInactivated; |
|
wait for cResetTime + 2 * cClkPeriod; |
|
for i in 0 to 31 loop |
FromController.DataBlock(128*i+127 downto 128 * i) <= X"FF00AA55884422110011223344556677"; |
end loop; |
FromController.Valid <= cActivated; |
FromController.Mode <= wide; |
|
wait until Clk = '1' and ToController.Ack = '1'; |
|
FromController.Mode <= standard; |
|
wait until Clk = '1'; |
wait until Clk = '1'; |
|
wait until Clk = '1' and ToController.Ack = '1'; |
|
FromController.DataBlock <= (others => '1'); |
|
wait until Clk = '1'; |
wait until Clk = '1'; |
|
wait until Clk = '1' and ToController.Ack = '1'; |
|
Finished <= cActivated; |
report "Finished" severity note; |
|
wait; |
end process Stimuli; |
|
SdData_inst: entity work.SdData |
port map ( |
iClk => Clk, |
inResetAsync => nResetAsync, |
iSdDataFromController => FromController, |
oSdDataToController => ToController, |
ioData => Data); |
|
end architecture Bhv; |
|
/src/grpSd/unitSdData/src/SdData-Rtl-a.vhdl
0,0 → 1,216
-- |
-- Title: Architecure of SdData |
-- File: SdData-Rtl-a.vhdl |
-- Author: Copyright 2010: Rainer Kastl |
-- Standard: VHDL'93 |
-- |
-- Description: |
-- |
|
architecture Rtl of SdData is |
|
type aState is (idle, send, receive); |
type aRegion is (startbit, data, crc, endbit); |
subtype aDataOutput is std_ulogic_vector(3 downto 0); |
|
subtype aByteCounter is unsigned(LogDualis(512)-1 downto 0); |
subtype aBitCounter is unsigned(LogDualis(8)-1 downto 0); |
|
type aReg is record |
State : aState; |
Region : aRegion; |
ByteCounter : aByteCounter; |
BitCounter : aBitCounter; |
Data : aDataOutput; |
Enable : std_ulogic; |
Controller : aSdDataToController; |
Mode : aSdDataBusMode; |
end record aReg; |
|
constant cDefaultReg : aReg := ( |
State => idle, |
Region => startbit, |
ByteCounter => to_unsigned(0, aByteCounter'length), |
BitCounter => to_unsigned(7, aBitCounter'length), |
Data => "0000", |
Enable => cInactivated, |
Controller => cDefaultSdDataToController, |
Mode => standard); |
|
type aCrcOut is record |
Clear : std_ulogic; |
DataIn : std_ulogic; |
Data : std_ulogic_vector(3 downto 0); |
end record aCrcOut; |
|
constant cDefaultCrcOut : aCrcOut := ( |
Clear => cInactivated, |
DataIn => cInactivated, |
Data => (others => '0')); |
|
type aCrcIn is record |
Correct : std_ulogic_vector(3 downto 0); |
Serial : std_ulogic_vector(3 downto 0); |
end record aCrcIn; |
|
signal CrcIn : aCrcIn; |
signal CrcOut : aCrcOut; |
signal CrcDataIn : std_ulogic_vector(3 downto 0); |
signal R, NextR : aReg; |
|
constant cSdStartBits : std_ulogic_vector(3 downto 0) := (others => cSdStartBit); |
constant cSdEndBits : std_ulogic_vector(3 downto 0) := (others => cSdEndBit); |
|
begin |
|
ioData <= "ZZZZ" when R.Enable = cInactivated else |
std_logic_vector(R.Data) when R.Mode = wide else |
"ZZZ" & R.Data(0); |
|
CrcDataIn <= (others => CrcOut.DataIn) when R.Mode = wide else |
"000" & CrcOut.DataIn; |
|
oSdDataToController <= R.Controller; |
|
Regs : process (iClk, inResetAsync) |
begin |
if (inResetAsync = cnActivated) then |
R <= cDefaultReg; |
elsif (iClk'event and iClk = cActivated) then |
R <= NextR; |
end if; |
end process Regs; |
|
Comb : process (ioData, iSdDataFromController, CrcIn, R) |
|
procedure SendBitAndShiftIntoCrc (constant data : in std_ulogic_vector(3 downto 0)) is |
begin |
CrcOut.Data <= data; |
CrcOut.DataIn <= cActivated; |
NextR.Data <= data; |
end procedure SendBitAndShiftIntoCrc; |
|
variable temp : std_ulogic_vector(3 downto 0); |
|
begin |
NextR <= R; |
NextR.Enable <= cInactivated; |
NextR.Controller.Ack <= cInactivated; |
NextR.Controller.Receiving <= cInactivated; |
NextR.Controller.Valid <= cInactivated; |
NextR.Controller.Busy <= cInactivated; |
NextR.Controller.Err <= cInactivated; |
CrcOut <= cDefaultCrcOut; |
|
case R.State is |
when idle => |
NextR.Mode <= iSdDataFromController.Mode; |
|
if (ioData = std_logic_vector(cSdStartBits)) then |
NextR.State <= receive; |
|
elsif (iSdDataFromController.Valid = cActivated) then |
NextR.State <= send; |
NextR.Region <= startbit; |
end if; |
|
when send => |
NextR.Enable <= cActivated; |
|
case R.Region is |
when startbit => |
SendBitAndShiftIntoCrc(cSdStartBits); |
NextR.Region <= data; |
|
when data => |
case R.Mode is |
when wide => |
for idx in 3 downto 0 loop |
temp(idx) := iSdDataFromController.DataBlock(to_integer(R.ByteCounter * 8 + R.BitCounter) - idx); |
end loop; |
|
SendBitAndShiftIntoCrc(temp); |
|
if (R.BitCounter = 3) then |
NextR.BitCounter <= to_unsigned(7, aBitCounter'length); |
|
if (R.ByteCounter = 511) then |
NextR.ByteCounter <= to_unsigned(0, aByteCounter'length); |
NextR.Region <= crc; |
|
else |
NextR.ByteCounter <= R.ByteCounter + 1; |
end if; |
|
else |
NextR.BitCounter <= R.BitCounter - 4; |
end if; |
|
when standard => |
temp := "000" & iSdDataFromController.DataBlock(to_integer(R.ByteCounter * 8 + R.BitCounter)); |
SendBitAndShiftIntoCrc(temp); |
|
if (R.BitCounter = 0) then |
NextR.BitCounter <= to_unsigned(7, aBitCounter'length); |
|
if (R.ByteCounter = 511) then |
NextR.ByteCounter <= to_unsigned(0, aByteCounter'length); |
NextR.Region <= crc; |
|
else |
NextR.ByteCounter <= R.ByteCounter + 1; |
end if; |
|
else |
NextR.BitCounter <= R.BitCounter - 1; |
end if; |
|
when others => |
report "Invalid SdData mode!" severity error; |
end case; |
|
when crc => |
NextR.data <= CrcIn.Serial; |
|
if (R.ByteCounter = 15) then |
NextR.ByteCounter <= to_unsigned(0, aByteCounter'length); |
NextR.Region <= endbit; |
|
else |
NextR.ByteCounter <= R.ByteCounter + 1; |
end if; |
|
when endbit => |
NextR.Controller.Ack <= cActivated; |
NextR.Data <= cSdEndBits; |
NextR.State <= idle; |
|
when others => |
report "Region not handled" severity error; |
end case; |
|
when others => |
report "State not handled" severity error; |
end case; |
end process Comb; |
|
crcs: for idx in 3 downto 0 generate |
|
CRC_inst : entity work.Crc |
generic map ( |
gPolynom => crc16 |
) |
port map ( |
iClk => iClk, |
inResetAsync => inResetAsync, |
iClear => CrcOut.Clear, |
iDataIn => CrcDataIn(idx), |
iData => CrcOut.Data(idx), |
oIsCorrect => CrcIn.Correct(idx), |
oSerial => CrcIn.Serial(idx) |
); |
|
end generate crcs; |
|
end architecture Rtl; |
|
/src/grpSd/unitSdData/src/SdData-e.vhdl
0,0 → 1,31
-- |
-- Title: SdData |
-- File: SdData-e.vhdl |
-- Author: Copyright 2010: Rainer Kastl |
-- Standard: VHDL'93 |
-- |
-- Description: Low level sending and receiving data |
-- SD Spec 2.00 |
-- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
use work.Global.all; |
use work.Sd.all; |
use work.CRCs.all; |
|
entity SdData is |
port ( |
iClk : in std_ulogic; |
inResetAsync : in std_ulogic; |
|
-- Controller |
iSdDataFromController : in aSdDataFromController; |
oSdDataToController : out aSdDataToController; |
|
-- Card |
ioData : inout std_logic_vector(3 downto 0) |
); |
end entity SdData; |
|
/src/grpSd/unitSdData/sim/SdData.tcl
0,0 → 1,2
source ../Files.tcl |
source ../../../sim/sim.tcl |
/src/grpSd/unitSdData/sim/wave.do
0,0 → 1,36
onerror {resume} |
quietly WaveActivateNextPane {} 0 |
add wave -noupdate -divider data |
add wave -noupdate -format Logic /tbsddata/sddata_inst/iclk |
add wave -noupdate -format Logic /tbsddata/sddata_inst/inresetasync |
add wave -noupdate -format Literal /tbsddata/sddata_inst/isddatafromcontroller |
add wave -noupdate -format Literal /tbsddata/sddata_inst/osddatatocontroller |
add wave -noupdate -format Literal /tbsddata/sddata_inst/iodata |
add wave -noupdate -format Literal /tbsddata/sddata_inst/crcin |
add wave -noupdate -format Literal /tbsddata/sddata_inst/crcout |
add wave -noupdate -format Literal -expand /tbsddata/sddata_inst/r |
add wave -noupdate -format Literal /tbsddata/sddata_inst/nextr |
add wave -noupdate -divider top |
add wave -noupdate -format Logic /tbsddata/clk |
add wave -noupdate -format Logic /tbsddata/nresetasync |
add wave -noupdate -format Logic /tbsddata/finished |
add wave -noupdate -format Literal /tbsddata/fromcontroller |
add wave -noupdate -format Literal /tbsddata/tocontroller |
add wave -noupdate -format Literal /tbsddata/data |
TreeUpdate [SetDefaultTree] |
WaveRestoreCursors {{Cursor 1} {40434 ns} 0} |
configure wave -namecolwidth 150 |
configure wave -valuecolwidth 100 |
configure wave -justifyvalue left |
configure wave -signalnamewidth 1 |
configure wave -snapdistance 10 |
configure wave -datasetprefix 0 |
configure wave -rowmargin 4 |
configure wave -childrowmargin 2 |
configure wave -gridoffset 0 |
configure wave -gridperiod 1 |
configure wave -griddelta 40 |
configure wave -timeline 0 |
configure wave -timelineunits ns |
update |
WaveRestoreZoom {40277 ns} {41944 ns} |
/src/grpSd/unitSdData/sim/SdData-unattended.tcl
0,0 → 1,3
set script SdData.tcl |
|
do "../../../sim/unattended.tcl" |
/src/grpSd/unitSdData/sim/Makefile
0,0 → 1,9
# Makefile for simulating wishbone slaves |
|
include ../../../../Makefile.rules |
|
all: SdData-unattended.sim |
|
clean: |
rm -rf vsim.wlf work |
|
/src/grpSd/unitSdData/syn/SdDatasyn.tcl
0,0 → 1,84
# Copyright (C) 1991-2010 Altera Corporation |
# Your use of Altera Corporation's design tools, logic functions |
# and other software and tools, and its AMPP partner logic |
# functions, and any output files from any of the foregoing |
# (including device programming or simulation files), and any |
# associated documentation or information are expressly subject |
# to the terms and conditions of the Altera Program License |
# Subscription Agreement, Altera MegaCore Function License |
# Agreement, or other applicable license agreement, including, |
# without limitation, that your use is for the sole purpose of |
# programming logic devices manufactured by Altera and sold by |
# Altera or its authorized distributors. Please refer to the |
# applicable agreement for further details. |
|
# Quartus II: Generate Tcl File for Project |
# File: SdCmdsyn.tcl |
# Generated on: Wed Jun 23 17:07:05 2010 |
|
# Load Quartus II Tcl Project package |
package require ::quartus::project |
package require ::quartus::flow |
|
set need_to_close_project 0 |
set make_assignments 1 |
|
# Check that the right project is open |
if {[is_project_open]} { |
if {[string compare $quartus(project) "SdDatasyn"]} { |
puts "Project SdDatasyn is not open" |
set make_assignments 0 |
} |
} else { |
# Only open if not already open |
if {[project_exists SdDatasyn]} { |
project_open -revision SdDatasyn SdDatasyn |
} else { |
project_new -revision SdDatasyn SdDatasyn |
} |
set need_to_close_project 1 |
} |
|
# Make assignments |
if {$make_assignments} { |
set_global_assignment -name FAMILY "Cyclone II" |
set_global_assignment -name DEVICE EP2C35F484C8 |
set_global_assignment -name TOP_LEVEL_ENTITY SdData |
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga |
|
source ../Files.tcl |
source ../../../syn/syn.tcl |
|
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top |
set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top |
set_global_assignment -name SMART_RECOMPILE ON |
set_global_assignment -name FMAX_REQUIREMENT "100 MHz" -section_id Clock |
set_global_assignment -name ENABLE_DRC_SETTINGS OFF |
set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF |
set_global_assignment -name USE_CONFIGURATION_DEVICE ON |
|
# Generate RBF |
set_global_assignment -name GENERATE_RBF_FILE ON |
set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION OFF |
|
source ../Pins.tcl |
|
set_instance_assignment -name CLOCK_SETTINGS Clock -to iClk |
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top |
|
# Commit assignments |
export_assignments |
|
# Compile project |
if {[catch {execute_flow -compile} result]} { |
puts "\nResult: $result\n" |
puts "ERROR: Compilation failed. See report files.\n" |
} else { |
puts "\nINFO: Compilation was successful.\n" |
} |
|
# Close project |
if {$need_to_close_project} { |
project_close |
} |
} |
src/grpSd/unitSdData/syn/SdDatasyn.tcl
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: src/grpSd/unitSdData/syn/Makefile
===================================================================
--- src/grpSd/unitSdData/syn/Makefile (nonexistent)
+++ src/grpSd/unitSdData/syn/Makefile (revision 92)
@@ -0,0 +1,9 @@
+# Makefile for synthesizing crcs
+
+include ../../../../Makefile.rules
+
+all: SdDatasyn.syn
+
+clean:
+ rm -rf db incremental_db *.rbf *.sof *.pin *.pof
+
Index: src/grpSd/unitSdData/Pins.tcl
===================================================================
--- src/grpSd/unitSdData/Pins.tcl (nonexistent)
+++ src/grpSd/unitSdData/Pins.tcl (revision 92)
@@ -0,0 +1,101 @@
+# Pin & Location Assignments
+# Signal Pin Pullup
+set pins {
+
+}
+
+# Set according to pins
+source ../../../syn/pins.tcl
+
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "AS INPUT TRI-STATED WITH WEAK PULL-UP"
+
+# #set_location_assignment PIN_B20 -to AVRAD[0]
+# #set_location_assignment PIN_A20 -to AVRAD[1]
+# #set_location_assignment PIN_B19 -to AVRAD[2]
+# #set_location_assignment PIN_A19 -to AVRAD[3]
+# #set_location_assignment PIN_B18 -to AVRAD[4]
+# #set_location_assignment PIN_A18 -to AVRAD[5]
+# #set_location_assignment PIN_B17 -to AVRAD[6]
+# #set_location_assignment PIN_A17 -to AVRAD[7]
+# #set_location_assignment PIN_A11 -to AVRADR[8]
+# #set_location_assignment PIN_A13 -to AVRADR[9]
+# #set_location_assignment PIN_B13 -to AVRADR[10]
+# #set_location_assignment PIN_A14 -to AVRADR[11]
+# #set_location_assignment PIN_B14 -to AVRADR[12]
+# #set_location_assignment PIN_A15 -to AVRADR[13]
+# #set_location_assignment PIN_B15 -to AVRADR[14]
+# #set_location_assignment PIN_A16 -to AVRADR[15]
+# #set_location_assignment PIN_B16 -to AVRALE
+# #set_location_assignment PIN_E15 -to AVRIRQ
+# #set_location_assignment PIN_B11 -to AVRRD
+# #set_location_assignment PIN_A10 -to AVRWR
+# #set_location_assignment PIN_C21 -to BCLK
+# #set_location_assignment PIN_D22 -to DIN
+# #set_location_assignment PIN_E22 -to DOUT
+# #set_location_assignment PIN_D21 -to LRCIN
+# #set_location_assignment PIN_E21 -to LRCOUT
+# #set_location_assignment PIN_E19 -to MCLK
+# set_location_assignment PIN_A12 -to iClk
+# #set_location_assignment PIN_AB11 -to iClk
+# #set_location_assignment PIN_C22 -to CS
+# set_location_assignment PIN_AB5 -to inKey1
+# set_location_assignment PIN_AA5 -to inKey2
+# set_location_assignment PIN_AB4 -to inKey3
+# set_location_assignment PIN_AA4 -to inKey4
+# set_location_assignment PIN_AB3 -to inKey5
+# set_location_assignment PIN_AA3 -to inKey6
+# set_location_assignment PIN_Y6 -to oSeg0
+# set_location_assignment PIN_W5 -to oSeg1
+# set_location_assignment PIN_Y5 -to oSeg2
+# set_location_assignment PIN_Y7 -to oSeg3
+# set_location_assignment PIN_V8 -to oSeg4
+# set_location_assignment PIN_W8 -to oSeg5
+# set_location_assignment PIN_Y9 -to oSeg6
+# set_location_assignment PIN_W7 -to oSeg7
+# set_location_assignment PIN_W4 -to oDIGIT_ADR_A
+# set_location_assignment PIN_Y4 -to oDIGIT_ADR_B
+# set_location_assignment PIN_Y3 -to oDIGIT_ADR_C
+# #set_location_assignment PIN_B4 -to Txd232
+# set_location_assignment PIN_Y20 -to inResetAsync
+# #set_location_assignment PIN_D5 -to Ps2Clk1
+# #set_location_assignment PIN_E7 -to Ps2Clk2
+# #set_location_assignment PIN_D4 -to Ps2Dat1
+# #set_location_assignment PIN_C4 -to Ps2Dat2
+# #set_location_assignment PIN_A4 -to Rxd232
+# #set_location_assignment PIN_W14 -to VgaBl0
+# #set_location_assignment PIN_Y14 -to VgaBl1
+# #set_location_assignment PIN_Y16 -to VgaGr0
+# #set_location_assignment PIN_W15 -to VgaGr1
+# #set_location_assignment PIN_V14 -to VgaHsync
+# #set_location_assignment PIN_Y17 -to VgaRd0
+# #set_location_assignment PIN_W16 -to VgaRd1
+# #set_location_assignment PIN_AA6 -to VgaVsync
+# #set_location_assignment PIN_C19 -to SCLK
+# #set_location_assignment PIN_C20 -to SDIN
+# #set_location_assignment PIN_AB7 -to mcoll_pad_i
+# #set_location_assignment PIN_AA7 -to mcrs_pad_i
+# #set_location_assignment PIN_W12 -to mrx_clk_pad_i
+# #set_location_assignment PIN_AA14 -to mrxd_pad_i[0]
+# #set_location_assignment PIN_AB15 -to mrxd_pad_i[1]
+# #set_location_assignment PIN_AA15 -to mrxd_pad_i[2]
+# #set_location_assignment PIN_AB16 -to mrxd_pad_i[3]
+# #set_location_assignment PIN_AB13 -to mrxdv_pad_i
+# #set_location_assignment PIN_AA13 -to mrxerr_pad_i
+# #set_location_assignment PIN_V12 -to mtx_clk_pad_i
+# #set_location_assignment PIN_AB9 -to mtxd_pad_o[0]
+# #set_location_assignment PIN_AA9 -to mtxd_pad_o[1]
+# #set_location_assignment PIN_AB8 -to mtxd_pad_o[2]
+# #set_location_assignment PIN_AA8 -to mtxd_pad_o[3]
+# #set_location_assignment PIN_AB12 -to mtxen_pad_o
+# #set_location_assignment PIN_AB14 -to mtxerr_pad_o
+# #set_location_assignment PIN_AB6 -to ETH_Reset_o
+# #set_location_assignment PIN_AB17 -to md_io
+# #set_location_assignment PIN_AA16 -to mdc_o
+#
+# set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to inKey1
+# set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to inKey2
+# set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to inKey3
+# set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to inKey4
+# set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to inKey5
+# set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to inKey6
+# set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to
Index: src/grpSd/pkgSd/src/Sd-p.vhdl
===================================================================
--- src/grpSd/pkgSd/src/Sd-p.vhdl (revision 91)
+++ src/grpSd/pkgSd/src/Sd-p.vhdl (revision 92)
@@ -103,24 +103,28 @@
subtype aSdRCA is std_ulogic_vector(15 downto 0);
constant cDefaultRCA : aSdRCA := (others => '0');
+ -- Data types
+ constant cBlocklen : natural := 512 * 8; -- 512 bytes
+ subtype aSdDataBlock is std_ulogic_vector(cBlocklen - 1 downto 0);
+
+ type aSdDataBusMode is (standard, wide);
+
-- Types for entities
+ -- between SdController and SdCmd
type aSdCmdFromController is record
- Content : aSdCmdContent;
- Valid : std_ulogic;
+ Content : aSdCmdContent; -- id and arg to sent to card
+ Valid : std_ulogic; -- gets asserted when Content is valid and can be sent to card
ExpectCID : std_ulogic; -- gets asserted when next response is R2
- CheckCrc : std_ulogic;
+ CheckCrc : std_ulogic; -- gets asserted when CRC has to be checked (exceptions is R3)
end record aSdCmdFromController;
type aSdCmdToController is record
- Ack : std_ulogic; -- Gets asserted when crc was sent, but endbit was
- -- not. This way we can minimize the wait time between sending 2 cmds.
- Receiving : std_ulogic;
- Content : aSdCmdContent;
- Valid : std_ulogic; -- gets asserted when CmdContent is valid (therefore
- -- a cmd was received)
- Err : std_ulogic; -- gets asserted when an error occurred during
- -- receiving a cmd
- Cid : aSdRegCID;
+ Ack : std_ulogic; -- Gets asserted when crc was sent, but endbit was not. This way we can minimize the wait time between sending 2 cmds.
+ Receiving : std_ulogic; -- gets asserted when a response is received currently
+ Content : aSdCmdContent; -- received id and arg, see valid
+ Valid : std_ulogic; -- gets asserted when CmdContent is valid (therefore a cmd was received and can be saved)
+ Err : std_ulogic; -- gets asserted when an error occurred during receiving a cmd, for example the crc check does not hold
+ Cid : aSdRegCID; -- received CID register of the card, see valid
end record aSdCmdToController;
constant cDefaultSdCmdToController : aSdCmdToController := (
@@ -131,11 +135,36 @@
Err => cInactivated,
Cid => cDefaultSdRegCID);
+ -- between SdController and SdData
+ type aSdDataFromController is record
+ Mode : aSdDataBusMode; -- select 1 bit or 4 bit mode
+ DataBlock : aSdDataBlock; -- DataBlock to send to card
+ Valid : std_ulogic; -- valid, when the datablock is valid and has to be sent
+ end record aSdDataFromController;
+
+ type aSdDataToController is record
+ Ack : std_ulogic; -- gets asserted when a datablock was sent to the card
+ Receiving : std_ulogic; -- gets asserted when a datablock is currently received
+ DataBlock : aSdDataBlock;
+ Valid : std_ulogic; -- gets asserted when DataBlock is valid and therefore it was received correctly
+ Busy : std_ulogic; -- gets asserted when the card returns busy
+ Err : std_ulogic; -- gets asserted when an error occurred during receiving a data block (CRC)
+ end record aSdDataToController;
+
+ constant cDefaultSdDataToController : aSdDataToController := (
+ Ack => cInactivated,
+ Receiving => cInactivated,
+ DataBlock => (others => '0'),
+ Valid => cInactivated,
+ Busy => cInactivated,
+ Err => cInactivated);
+
+ -- between SdController and wishbone interface
type aSdRegisters is record
CardStatus : aSdCardStatus;
end record aSdRegisters;
- -- constants for Controller
+ -- constants for SdController
subtype aRCA is std_ulogic_vector(15 downto 0);
constant cSdDefaultRCA : aRCA := (others => '0');
/src/grpSd/unitSdCmd/src/SdCmd-Rtl-ea.vhdl
1,11 → 1,14
------------------------------------------------- |
-- file: SdCmd-ea.vhdl |
-- author: Rainer Kastl |
-- |
-- Low level sending commands and receiving responses |
-- Title: SdCmd |
-- File: SdCmd-Rtl-ea.vhdl |
-- Author: Copyright 2010: Rainer Kastl |
-- Standard: VHDL'93 |
-- |
-- Description: Low level sending commands and receiving responses |
-- SD Spec 2.00 |
------------------------------------------------- |
-- |
|
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
/src/grpCrc/pkgCRCs/src/CRCs-p.vhdl
3,8 → 3,13
|
package CRCs is |
|
constant crc7 : std_ulogic_vector(7 downto 0) := B"1000_1001"; |
constant crc16 : std_ulogic_vector(16 downto 0) := (16 => '1', 12 => '1', |
5 => '1', 0 => '1', others => '0'); |
constant crc7 : std_ulogic_vector(7 downto 0) := B"1000_1001"; |
constant crc16 : std_ulogic_vector(16 downto 0) := ( |
16 => '1', |
12 => '1', |
5 => '1', |
0 => '1', |
others => '0'); |
|
|
end package CRCs; |
/Makefile
1,8 → 1,8
# Recursive makefile for simulations |
|
SIMS = grpCrc/unitCrc grpWishbone/unitWbSlave grpSd/unitSdCmd grpSd/unitSdCardModel grpStrobesClocks/unitTimeoutGenerator grpRs232/unitRs232Tx |
SIMS = grpCrc/unitCrc grpWishbone/unitWbSlave grpSd/unitSdCmd grpSd/unitSdCardModel grpStrobesClocks/unitTimeoutGenerator grpRs232/unitRs232Tx grpSd/unitSdData |
SYSVSIMS = grpSd/unitSdVerificationTestbench |
SYNS = grpCrc/unitCrc grpSd/unitSdCmd grpSd/unitSdTop grpSd/unitTbdSd |
SYNS = grpCrc/unitCrc grpSd/unitSdCmd grpSd/unitSdTop grpSd/unitTbdSd grpSd/unitSdData |
|
sim: |
for i in $(SIMS); do make -C src/$$i/sim; done |