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URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /sdhc-sc-core
    from Rev 156 to Rev 157
    ↔ Reverse comparison
  •

Rev 156 → Rev 157

/trunk/src/grpSd/unitSdCardModel/src/SdBFM-impl.sv
43,12 → 43,12
task SdBFM::sendAllDataBlocks(SdDataBlock blocks[]);
foreach(blocks[i]) begin
sendDataBlock(blocks[i]);
waitUntilReady();
//waitUntilReady(); // TODO: check pauses between transactions on the bus without waits
end
endtask
 
task SdBFM::waitUntilReady();
repeat (8) @ICard.cb;
//repeat (8) @ICard.cb;
endtask
 
task SdBFM::sendDataBlock(SdDataBlock block);
182,7 → 182,6
aCrc16 crc[4];
block = new();
 
$display("Startbits: %t", $time);
for (int j = 0; j <= 512*2; j++) begin
@ICard.cb;
for(int i = 0; i < 4; i++) begin
202,7 → 201,6
 
// end bits
@ICard.cb;
$display("Endbits: %h, %t", ICard.cb.Data, $time);
assert(ICard.cb.Data == 'b1111);
endtask
 
234,7 → 232,7
task SdBFM::start();
fork
begin
run();
//run();
end
join_none
endtask
/trunk/src/grpSd/unitSdCardModel/src/SdCardModel.sv
23,7 → 23,7
SdBfmMb SdTransOutMb;
SdBfmMb SdTransInMb;
 
local SdBFM bfm;
SdBFM bfm;
local SdCardModelState state;
local RCA_t rca;
local logic CCS;
50,8 → 50,11
log = new();
endfunction
 
function void start();
endfunction
task start();
fork
run();
join_none
endtask
 
task reset();
endtask
218,6 → 221,7
response = new(cSdCmdSendStatus, state);
this.bfm.send(response);
 
log.note("Card init done");
endtask
 
task run();
/trunk/src/grpSd/unitSdWbSlave/src/WbTransaction.sv
2,7 → 2,7
`ifndef WBTRANSACTION_SV
`define WBTRANSACTION_SV
 
typedef bit[3:0] WbAddr;
typedef bit[2:0] WbAddr;
typedef bit[31:0] WbData;
 
class WbTransaction;
18,6 → 18,10
function void display();
$display("Transaction: %s, %s, %b, %b", Type.name(), Kind.name(), Addr, Data);
endfunction
 
constraint NotImplementedYet {
Type == Classic;
};
endclass
 
class WbTransactionSequence;
/trunk/src/grpSd/unitSdWbSlave/src/IWishboneBus.sv
13,7 → 13,7
logic ERR_I;
logic RTY_I;
logic CLK_I = 1;
logic RST_I;
logic RST_I = 1;
logic ACK_I;
logic [`cWishboneWidth-1 : 0] DAT_I;
 
/trunk/src/grpSd/unitSdWbSlave/src/WishboneBFM.sv
11,6 → 11,7
 
`include "IWishboneBus.sv";
`include "WbTransaction.sv";
`include "Logger.sv";
 
class WbBFM;
 
17,16 → 18,50
virtual IWishboneBus.Master Bus;
WbTransMb TransInMb;
WbTransMb TransOutMb;
int StopAfter = -1;
Logger Log = new();
 
function new(virtual IWishboneBus.Master Bus);
this.Bus = Bus;
endfunction
 
function void start();
endfunction
task start();
fork
this.run();
join_none;
endtask
 
task run();
Idle();
 
while (StopAfter != 0) begin
WbTransaction transaction;
 
TransInMb.get(transaction);
case (transaction.Type)
WbTransaction::Classic: begin
case (transaction.Kind)
WbTransaction::Read: begin
Read(transaction.Addr, transaction.Data);
end
WbTransaction::Write: begin
Write(transaction.Addr, transaction.Data);
end
endcase
end
default: begin
string msg;
$swrite(msg, "Transaction.Type %s not handled.", transaction.Type.name());
Log.error(msg);
end
endcase
if (StopAfter > 0) StopAfter--;
end
endtask
 
task Idle();
 
@(posedge this.Bus.CLK_I)
this.Bus.cbMaster.CYC_O <= cNegated;
this.Bus.cbMaster.ADR_O <= '{default: cDontCare};
39,8 → 74,7
this.Bus.cbMaster.WE_O <= cDontCare;
this.Bus.cbMaster.LOCK_O <= cNegated;
this.Bus.cbMaster.CTI_O <= '{default: cDontCare};
$display("%t : Bus idle.", $time);
 
Log.note("WbBus idle");
endtask;
 
function void checkResponse();
47,16 → 81,16
 
// Analyse slave response
if (this.Bus.cbMaster.ERR_I == cAsserted) begin
$display("%t : MasterWrite: ERR_I asserted; Slave encountered an error.", $time);
Log.error("MasterWrite: ERR_I asserted; Slave encountered an error.");
end
if (this.Bus.cbMaster.RTY_I == cAsserted) begin
$display("%t : MasterWrite: RTY_I asserted; Retry requested.", $time);
Log.note("MasterWrite: RTY_I asserted; Retry requested.");
end
 
endfunction;
 
task Read(logic [`cWishboneWidth-1 : 0] Address,
ref logic [`cWishboneWidth-1 : 0] Data,
ref bit [`cWishboneWidth-1 : 0] Data,
input logic [`cWishboneWidth-1 : 0] TGA = '{default: cDontCare},
input logic [`cWishboneWidth-1 : 0] BankSelect = '{default: 1});
 
79,7 → 113,11
checkResponse();
 
Data = this.Bus.cbMaster.DAT_I; // latch it before the CLOCK???
//$display("%t : Reading %h", $time, Data);
begin
string msg;
$swrite(msg, "WbBus: Reading %h", Data);
Log.note(msg);
end
 
this.Bus.cbMaster.STB_O <= cNegated;
this.Bus.cbMaster.CYC_O <= cNegated;
197,7 → 235,7
task TestSingleOps (logic [`cWishboneWidth-1 : 0] Address,
logic [`cWishboneWidth-1 : 0] Data);
 
logic [`cWishboneWidth-1 : 0] rd;
bit [`cWishboneWidth-1 : 0] rd;
 
this.Write(Address, Data);
this.Read(Address, rd);
/trunk/src/grpSd/unitSdData/src/SdData-Rtl-a.vhdl
193,7 → 193,7
 
end if;
else
if (RByteC = 0 and RBitC = 7 and R.WordInvalid = cInactivated) then
if (RByteC = 0 and RBitC = 7 and R.WordInvalid = cInactivated and iSdDataFromController.DisableRb = cInactivated) then
-- received word is valid, save it to ram
NextR.WriteReadFifo.data <= R.Word;
HandleFifoAccess(iWriteReadFifo.wrfull, NextR.WriteReadFifo.wrreq);
407,16 → 407,18
 
when crc =>
-- save last word to ram
HandleFifoAccess(iWriteReadFifo.wrfull, NextR.WriteReadFifo.wrreq);
NextR.WriteReadFifo.data <= R.Word;
 
ShiftIntoCrc(std_ulogic_vector(iData.Data));
 
if (R.Counter = 15) then
-- all 16 crc bits received
-- all 16 crc bits received
NextR.Region <= endbit;
else
NextR.Counter <= R.Counter + 1;
 
if (R.Counter = 0 and iSdDataFromController.DisableRb = cInactivated) then
HandleFifoAccess(iWriteReadFifo.wrfull, NextR.WriteReadFifo.wrreq);
NextR.WriteReadFifo.data <= R.Word;
end if;
end if;
 
when endbit =>
/trunk/src/grpSd/pkgSd/src/Sd-p.vhdl
172,6 → 172,7
ExpectBits : aSdDataBits; -- how many bits are expected in wide with data mode
Valid : std_ulogic; -- valid, when the datablock is valid and has to be sent
CheckBusy : std_ulogic; -- check for busy signaling
DisableRb : std_ulogic; -- disable read back: do not save read data to fifo
end record aSdDataFromController;
 
constant cDefaultSdDataFromController : aSdDataFromController := (
179,7 → 180,8
DataMode => usual,
ExpectBits => ScrBits,
Valid => cInactivated,
CheckBusy => cInactivated);
CheckBusy => cInactivated,
DisableRb => cActivated);
 
type aSpeedBits is record
HighSpeedSupported : std_ulogic;
/trunk/src/grpSd/unitSdVerificationTestbench/src/SdVerificationTestbench.sv
32,7 → 32,7
harness.Card = card;
 
harness.start();
#1ms;
#2ms;
 
log.terminate();
end
72,6 → 72,7
 
initial begin
#10 nResetAsync <= 1;
#10 IWbBus.RST_I <= 0;
end
 
Test tb(CardInterface, IWbBus);
/trunk/src/grpSd/unitSdVerificationTestbench/src/Harness.sv
64,6 → 64,9
Card.SdTransOutMb = new(1);
Card.SdTransInMb = new(1);
 
// todo: remove
Card.bfm = SdBfm;
 
// connect Mailboxes
TransFunc.TransInMb = TransSeqGen.TransOutMb[0];
TransBfm.SdTransInMb = TransSeqGen.TransOutMb[1];
/trunk/src/grpSd/unitSdVerificationTestbench/sim/wave.do
1,6 → 1,28
onerror {resume}
quietly WaveActivateNextPane {} 0
WaveRestoreCursors {{Cursor 1} {2020 ns} 0} {{Cursor 2} {10084945 ns} 0} {{Cursor 3} {10085095 ns} 0}
add wave -noupdate -format Logic /Testbed/CardInterface/Cmd
add wave -noupdate -format Logic /Testbed/CardInterface/SClk
add wave -noupdate -format Literal /Testbed/CardInterface/Data
add wave -noupdate -format Logic /Testbed/IWbBus/ERR_I
add wave -noupdate -format Logic /Testbed/IWbBus/RTY_I
add wave -noupdate -format Logic /Testbed/IWbBus/CLK_I
add wave -noupdate -format Logic /Testbed/IWbBus/RST_I
add wave -noupdate -format Logic /Testbed/IWbBus/ACK_I
add wave -noupdate -format Literal /Testbed/IWbBus/DAT_I
add wave -noupdate -format Logic /Testbed/IWbBus/CYC_O
add wave -noupdate -format Literal /Testbed/IWbBus/ADR_O
add wave -noupdate -format Literal /Testbed/IWbBus/DAT_O
add wave -noupdate -format Logic /Testbed/IWbBus/SEL_O
add wave -noupdate -format Logic /Testbed/IWbBus/STB_O
add wave -noupdate -format Literal /Testbed/IWbBus/TGA_O
add wave -noupdate -format Literal /Testbed/IWbBus/TGC_O
add wave -noupdate -format Logic /Testbed/IWbBus/TGD_O
add wave -noupdate -format Logic /Testbed/IWbBus/WE_O
add wave -noupdate -format Logic /Testbed/IWbBus/LOCK_O
add wave -noupdate -format Literal /Testbed/IWbBus/CTI_O
add wave -noupdate -format Literal /Testbed/IWbBus/BTE_O
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {2518 ns} 0} {{Cursor 2} {10084945 ns} 0} {{Cursor 3} {10085095 ns} 0}
configure wave -namecolwidth 150
configure wave -valuecolwidth 100
configure wave -justifyvalue left
/trunk/src/grpSd/unitSdController/src/SdController-Rtl-a.vhdl
659,6 → 659,7
 
when requestnewoperation =>
 
NextR.ToSdData.DisableRb <= cInactivated;
NextR.ToSdWbSlave.ReqOperation <= not R.ToSdWbSlave.ReqOperation;
NextR.State <= idle;
 
/trunk/src/grpSdVerification/unitSdCoreTransactionBFM/src/SdCoreTransactionBFM.sv
32,6 → 32,7
SdCoreTransaction::readSingleBlock:
begin
WbTransactionSequenceReadSingleBlock tmp = new(trans.startAddr, trans.endAddr);
assert (tmp.randomize()) else Log.error("Randomizing WbTransactionSequence seq failed.");
seq = tmp;
end
default:
42,11 → 43,9
end
endcase
 
assert (seq.randomize()) else Log.error("Randomizing WbTransactionSequence seq failed.");
seq.display();
 
foreach(seq.transactions[i])
foreach(seq.transactions[i]) begin
WbTransOutMb.put(seq.transactions[i]);
end
 
if (StopAfter > 0) StopAfter--;
end
/trunk/src/grpSdVerification/unitSdCoreTransactionBFM/src/WbTransactionReadSingleBlock.sv
10,7 → 10,7
WbAddr EndAddr;
 
function new(WbAddr StartAddr, WbAddr EndAddr);
size = 1 + 1 + 1; // startaddr, endaddr, operation
size = 1 + 1 + 1 + 512*8/32; // startaddr, endaddr, operation, read data back
transactions = new[size];
foreach(transactions[i])
24,7 → 24,8
transactions[2].Addr == cOperationAddr;
transactions[2].Data == cOperationRead;
 
transactions[0].Addr == cStartAddrAddr || cEndAddrAddr;
transactions[0].Addr == cStartAddrAddr ||
transactions[0].Addr == cEndAddrAddr;
if (transactions[0].Addr == cStartAddrAddr) {
transactions[1].Addr == cEndAddrAddr;
transactions[1].Data == EndAddr;
40,6 → 41,7
transactions[i].Kind == WbTransaction::Write;
} else {
transactions[i].Kind == WbTransaction::Read;
transactions[i].Addr == cReadDataAddr;
}
}
};
/trunk/src/grpSdVerification/unitSdCoreTransferFunction/src/SdCoreTransferFunction.sv
23,7 → 23,6
SdCoreTransaction transaction;
 
TransInMb.get(transaction);
Log.note("SdCoreTransferFunction transaction received");
 
if (StopAfter > 0) StopAfter--;
end

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