OpenCores
URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

Compare Revisions

  • This comparison shows the changes necessary to convert path 
    /sdhc-sc-core
    from Rev 158 to Rev 159
    ↔ Reverse comparison
  •

Rev 158 → Rev 159

/trunk/src/grpSd/unitSdCardModel/src/SdBFM-impl.sv
184,7 → 184,7
 
for (int j = 0; j < 512*2; j++) begin
@ICard.cb;
for(int i = 0; i < 4; i++) begin
for(int i = 3; i >= 0; i--) begin
block.data.push_back(ICard.cb.Data[i]);
end
end
192,7 → 192,7
// crc
for (int j = 0; j < 16; j++) begin
@ICard.cb;
for(int i = 0; i < 4; i++) begin
for(int i = 3; i >= 0; i--) begin
crc[i] = ICard.cb.Data[i];
end
end
/trunk/src/grpSd/unitSdCardModel/src/SdCardModel.sv
32,14 → 32,14
local Logger log;
 
 
local rand int datasize; // ram addresses = 2^datasize - 1; 512 byte blocks
constraint cdatasize {datasize > 1; datasize <= 32;}
//local rand int datasize; // ram addresses = 2^datasize - 1; 512 byte blocks
//constraint cdatasize {datasize == 32;}
 
local bit[512*8-1:0] ram[];
local bit[0:511][7:0] ram[];
function void post_randomize() ;
this.ram = new[2^(datasize-1)];
endfunction
/*function void post_randomize() ;
this.ram = new[datasize];
endfunction*/
 
function new();
//this.bfm = bfm;
48,6 → 48,7
rca = 0;
mode = standard;
log = new();
ram = new[100];
endfunction
 
task start();
249,15 → 250,17
 
// expect Read
assert(token.id == cSdCmdReadSingleBlock);
addr = token.arg[0];
assert(addr < ram.size());
addr = token.arg;
assert(addr <= ram.size()) else log.error("Read outside of available RAM");
response = new(cSdCmdReadSingleBlock, state);
response.DataBlocks = new[1];
response.DataBlocks[0] = new();
//$display("Ram before read (%h): %h", addr, ram[addr]);
 
for (int i = 0; i < 512; i++) begin
for (int j = 7; j >= 0; j--) begin
response.DataBlocks[0].data.push_back(ram[addr][i*8 + j]);
response.DataBlocks[0].data.push_back(ram[addr][i][j]);
end
end
 
272,7 → 275,7
// expect Write
assert(token.id == cSdCmdWriteSingleBlock);
addr = token.arg;
assert(addr < ram.size());
assert(addr <= ram.size()) else log.error("Write outside of available RAM");
response = new(cSdCmdWriteSingleBlock, state);
this.bfm.send(response);
 
286,7 → 289,8
// write into ram
for (int i = 0; i < 512; i++) begin
for (int j = 7; j >= 0; j--) begin
ram[addr][i * 8 + j] = rdblock.data.pop_front();
//$display("rd_front: %d", rdblock.data[0:7]);
ram[addr][i][j] = rdblock.data.pop_front();
end
end
 
293,7 → 297,11
this.bfm.waitUntilReady();
this.bfm.sendBusy();
//$display("Ram at write address: %h", ram[addr]);
//$display("Ram after write (%h): %h", addr, ram[addr]);
/*$display("Ram after write (%h):", addr);
for(int i = 0; i < 512; i++) begin
$display("idx %d: %d", i, ram[addr][i]);
end*/
 
endtask
 
/trunk/src/grpSdVerification/unitSdCoreChecker/src/SdCoreChecker.sv
97,7 → 97,10
SdCoreTransactions.sample();
 
if (res.trans.compare(trans) == 1) begin
string msg;
Log.note("Checker: Transaction successful");
$swrite(msg, "%s", trans.toString());
Log.note(msg);
end
else begin
string msg;
/trunk/src/grpSdVerification/unitSdCoreTransaction/src/SdCoreTransaction.sv
27,8 → 27,8
kind == readSingleBlock ||
kind == writeSingleBlock;
 
startAddr inside {[0:1000]};
endAddr inside {[0:1000]};
startAddr inside {[0:31]};
endAddr inside {[0:31]};
};
 
function SdCoreTransaction copy();
59,18 → 59,25
 
rand SdCoreTransaction transactions[];
 
function new();
transactions = new[100];
foreach(transactions[i]) transactions[i] = new();
endfunction
 
constraint randlength {
transactions.size() > 0;
transactions.size() <= 100;
 
foreach(transactions[i]) {
if (i % 2 == 0) {
transactions[i].kind == SdCoreTransaction::writeSingleBlock;
} else {
transactions[i].kind == SdCoreTransaction::readSingleBlock;
transactions[i].startAddr == transactions[i-1].startAddr;
}
}
}
 
function void post_randomize();
foreach (transactions[i]) begin
transactions[i] = new();
assert(transactions[i].randomize());
end
endfunction
endclass
 
typedef mailbox #(SdCoreTransaction) SdCoreTransSeqMb;
/trunk/src/grpSdVerification/unitSdCoreTransactionBFM/src/SdCoreTransactionBFM.sv
32,22 → 32,29
case (trans.kind)
SdCoreTransaction::readSingleBlock:
begin
int j = 0;
string msg;
WbTransactionSequenceReadSingleBlock tmp = new(trans.startAddr, trans.endAddr);
$swrite(msg, "Addresses: in: %h, %h, out: %h, %h", trans.startAddr, trans.endAddr, tmp.StartAddr, tmp.EndAddr);
assert (tmp.randomize()) else Log.error("Randomizing WbTransactionSequence seq failed.");
seq = tmp;
 
trans.data = new[1];
 
Log.note(msg);
 
foreach(seq.transactions[i]) begin
WbTransaction tr;
int j = 0;
 
WbTransOutMb.put(seq.transactions[i]);
WbTransInMb.get(tr);
 
// receive read data
if (tr.Kind == WbTransaction::Read && tr.Addr == cReadDataAddr) begin
trans.data[j++] = tr.Data[7:0];
trans.data[j++] = tr.Data[15:8];
trans.data[j++] = tr.Data[23:16];
trans.data[j++] = tr.Data[31:24];
trans.data[0][j++] = tr.Data[31:24];
trans.data[0][j++] = tr.Data[23:16];
trans.data[0][j++] = tr.Data[15:8];
trans.data[0][j++] = tr.Data[7:0];
end
end
/trunk/src/grpSdVerification/unitSdCoreTransactionBFM/src/WbTransactionWriteSingleBlock.sv
7,11 → 7,11
 
class WbTransactionSequenceWriteSingleBlock extends WbTransactionSequence;
 
WbAddr StartAddr;
WbAddr EndAddr;
WbData StartAddr;
WbData EndAddr;
WbData Data[$];
 
function new(WbAddr StartAddr, WbAddr EndAddr, DataBlock Datablock);
function new(WbData StartAddr, WbData EndAddr, DataBlock Datablock);
size = 1 + 1 + 1 + 512*8/32; // startaddr, endaddr, operation, write data
transactions = new[size];
/trunk/src/grpSdVerification/unitSdCoreTransactionBFM/src/WbTransactionReadSingleBlock.sv
6,10 → 6,10
 
class WbTransactionSequenceReadSingleBlock extends WbTransactionSequence;
 
WbAddr StartAddr;
WbAddr EndAddr;
WbData StartAddr;
WbData EndAddr;
 
function new(WbAddr StartAddr, WbAddr EndAddr);
function new(WbData StartAddr, WbData EndAddr);
size = 1 + 1 + 1 + 512*8/32; // startaddr, endaddr, operation, read data back
transactions = new[size];

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.