URL
https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk
Subversion Repositories sdhc-sc-core
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- This comparison shows the changes necessary to convert path
/sdhc-sc-core
- from Rev 166 to Rev 167
- ↔ Reverse comparison
Rev 166 → Rev 167
/trunk/src/grpSd/unitSdCardModel/src/SdBFM-impl.sv
129,11 → 129,26
endtask |
|
task SdBFM::sendBusy(); |
repeat (2) @ICard.cb; |
|
@ICard.cb; |
|
ICard.cb.Data[0] <= 0; |
|
// send valid status |
@ICard.cb; |
ICard.cb.Data[0] <= 0; |
@ICard.cb; |
ICard.cb.Data[0] <= 1; |
@ICard.cb; |
ICard.cb.Data[0] <= 0; |
|
// endbit |
@ICard.cb; |
ICard.cb.Data[0] <= 1; |
|
// 10 busy cycles |
@ICard.cb; |
ICard.cb.Data[0] <= 0; |
|
repeat (10) @ICard.cb; |
ICard.cb.Data[0] <= 1; |
|
/trunk/src/grpSd/unitSdCardModel/src/SdCardModel.sv
58,7 → 58,10
end |
end |
|
RamActionOutMb.put(action); |
if (RamActionOutMb != null) |
begin |
RamActionOutMb.put(action); |
end |
endtask |
|
task setDataBlock(logic[31:0] addr, SdDataBlock block); |
/trunk/src/grpSd/unitTestWbMaster/src/TestWbMaster-e.vhdl
51,8 → 51,7
SEL_O : out std_ulogic_vector(0 downto 0); |
|
-- status signal |
ERR_O : out std_ulogic; |
DON_O : out std_ulogic |
LEDBANK_O : out std_ulogic_vector(7 downto 0) |
); |
end entity TestWbMaster; |
|
/trunk/src/grpSd/unitTestWbMaster/src/TestWbMaster-Rtl-a.vhdl
37,6 → 37,8
Counter : aCounter; |
WbState : aWbState; |
Err : std_ulogic; |
ReadData : unsigned(31 downto 0); |
StartAddr: unsigned(31 downto 0); |
|
end record aReg; |
|
44,6 → 46,9
|
begin |
|
LEDBANK_O(7) <= R.Err; |
LEDBANK_O(2 downto 0) <= std_ulogic_vector(R.StartAddr(2 downto 0)); |
|
Regs : process (CLK_I) |
begin |
if (rising_edge(CLK_I)) then |
54,6 → 59,8
R.Counter <= (others => '0'); |
R.WbState <= write; |
R.Err <= '0'; |
R.ReadData <= (others => '0'); |
R.StartAddr <= X"00000000"; |
|
else |
R <= NxR; |
68,7 → 75,6
|
-- default assignment |
NxR <= R; |
ERR_O <= R.Err; |
CTI_O <= "000"; |
CYC_O <= '0'; |
WE_O <= '0'; |
77,7 → 83,7
ADR_O <= "000"; |
DAT_O <= (others => '0'); |
BTE_O <= "00"; |
DON_O <= '0'; |
LEDBANK_O(6 downto 3) <= (others => '0'); |
|
-- we don´t care for errors or retrys |
if (ERR_I = '1' or RTY_I = '1') then |
112,20 → 118,6
SEL_O <= "1"; |
STB_O <= '1'; |
|
if (ACK_I = '1') then |
-- check data |
--if to_unsigned(to_integer(DAT_I),32) /= to_unsigned(R.Counter, 32) then |
-- NxR.Err <= '1'; |
--end if; |
|
if (R.Counter = 128) then |
NxR.Counter <= (others => '0'); |
NxR.WbState <= idle; |
else |
NxR.Counter <= R.Counter + 1; |
end if; |
end if; |
|
when others => |
report "Invalid wbState" severity error; |
end case; |
133,10 → 125,10
case R.State is |
when startAddr => |
ADR_O <= "001"; |
DAT_O <= X"00000004"; |
DAT_O <= std_ulogic_vector(R.startAddr); |
|
if (ACK_I = '1') then |
NxR.State <= writeBuffer; |
NxR.State <= read; |
NxR.Counter <= (others => '0'); |
NxR.WbState <= write; |
end if; |
143,25 → 135,37
|
when writeBuffer => |
ADR_O <= "100"; -- write data |
DAT_O <= std_ulogic_vector(R.Counter) & std_ulogic_vector(R.Counter) & |
std_ulogic_vector(R.Counter) & std_ulogic_vector(R.Counter); |
DAT_O <= std_ulogic_vector(R.ReadData + 1); |
|
if (R.Counter = 128) then |
NxR.State <= write; |
NxR.Counter <= to_unsigned(128, aCounter'length); |
NxR.WbState <= write; |
if (ACK_I = '1') then |
if (R.Counter = 128) then |
NxR.State <= write; |
NxR.Counter <= to_unsigned(128, aCounter'length); |
NxR.WbState <= write; |
else |
NxR.State <= readBuffer; |
NxR.WbState <= read; |
end if; |
end if; |
|
when write => |
LEDBANK_O(3) <= '1'; |
ADR_O <= "000"; |
DAT_O <= X"00000010"; -- start write operation |
|
if (ACK_I = '1') then |
NxR.State <= done; |
NxR.State <= startAddr; |
NxR.WbState <= write; |
NxR.startAddr <= R.startAddr + 1; |
end if; |
|
if (R.StartAddr = 4) then |
NxR.State <= done; |
NxR.WbState <= idle; |
end if; |
|
when read => |
LEDBANK_O(4) <= '1'; |
ADR_O <= "000"; |
DAT_O <= X"00000001"; -- start read operation |
|
171,16 → 175,18
end if; |
|
when readBuffer => |
LEDBANK_O(5) <= '1'; |
ADR_O <= "011"; -- read data |
|
if (R.Counter = 128) then |
NxR.Counter <= (others => '0'); |
NxR.State <= done; |
NxR.WbState <= idle; |
if (ACK_I = '1') then |
NxR.ReadData <= unsigned(DAT_I); |
NxR.State <= writeBuffer; |
NxR.WbState <= write; |
end if; |
|
when done => |
DON_O <= '1'; |
LEDBANK_O(6) <= '1'; |
report "End of Simulation" severity failure; |
|
when others => |
report "Invalid state" severity error; |
/trunk/src/grpSd/unitSdWbSlave/src/SdWbSlave-Rtl-a.vhdl
52,7 → 52,7
SdIntState => idle, |
OperationBlock => cDefaultOperationBlock, |
ReqOperation => cInactivated, |
oWbDat => (Dat => (others => '0')), |
oWbDat => (Dat => (others => 'X')), |
oWbCtrl => cDefaultWbSlaveCtrlOutput, |
oController => cDefaultSdWbSlaveToSdController, |
oWriteFifo => cDefaultoWriteFifo, |
234,6 → 234,8
|
when others => |
report "Write to an invalid address" severity warning; |
NxR.oWbCtrl.Err <= cActivated; |
NxR.oWbCtrl.Ack <= cInactivated; |
end case; |
end if; |
|
/trunk/src/grpSd/unitSdData/src/SdData-Rtl-a.vhdl
26,10 → 26,12
|
architecture Rtl of SdData is |
|
type aState is (idle, send, receive, checkbusy); -- overall states |
type aState is (idle, send, receive, crcstatus, checkbusy); -- overall states |
type aRegion is (startbit, data, crc, endbit); -- regions in send and receive state |
subtype aCounter is unsigned(LogDualis(512*8)-1 downto 0); -- bit counter |
|
subtype aCrcStatus is std_ulogic_vector(2 downto 0); |
|
-- all registers |
type aReg is record |
State : aState; |
47,6 → 49,7
ReadWriteFifo : aoReadFifo; |
WriteReadFifo : aoWriteFifo; |
DisableSdClk : std_ulogic; |
CrcStatus : aCrcStatus; |
end record aReg; |
|
-- default value for registers |
61,7 → 64,8
Controller => cDefaultSdDataToController, |
ReadWriteFifo => cDefaultoReadFifo, |
WriteReadFifo => cDefaultoWriteFifo, |
DisableSdClk => cInactivated); |
DisableSdClk => cInactivated, |
CrcStatus => (others => '0')); |
|
type aCrcOut is record |
DataIn : std_ulogic; |
266,12 → 270,10
when idle => |
-- check if card signals that it is busy (the controller has to enable this check) |
if (iSdDataFromController.CheckBusy = cActivated) then |
if (iData.Data(0) = cInactivated) then |
-- NextR.Controller.Busy <= cActivated; |
end if; |
NextR.State <= crcstatus; |
NextR.Region <= startbit; |
NextR.Counter <= (others => '0'); |
|
NextR.State <= checkbusy; |
|
elsif (R.Mode = wide and iData.Data = cSdStartBits) or (R.Mode = standard and iData.Data(0) = cSdStartBit) then |
-- start receiving |
NextR.Region <= data; |
313,6 → 315,32
NextR.Mode <= iSdDataFromController.Mode; |
end if; |
|
when crcstatus => |
case R.Region is |
when startbit => |
if (iData.Data(0) = cSdStartBit) then |
NextR.Region <= data; |
end if; |
|
when data => |
NextR.CrcStatus(to_integer(R.Counter)) <= iData.Data(0); |
NextR.Counter <= R.Counter + 1; |
|
if (R.Counter = 2) then |
NextR.Region <= endbit; |
end if; |
|
when endbit => |
if (R.CrcStatus /= "010") then |
NextR.Controller.Err <= cActivated; |
NextR.State <= idle; |
else |
NextR.State <= checkbusy; |
end if; |
when others => |
report "Invalid state reached" severity error; |
end case; |
|
when checkbusy => |
NextR.Controller.Busy <= cActivated; |
|
/trunk/src/grpSd/unitTbdSd/src/TbdSd-Rtl-ea.vhdl
78,12 → 78,12
signal oErr : std_ulogic; |
signal oRty : std_ulogic; |
|
signal ErrorLed, DoneLed : std_ulogic; |
signal LedBank : std_ulogic_vector(7 downto 0); |
signal LedBank2 : std_ulogic_vector(7 downto 0); |
|
begin |
|
oLedBank <= LedBank(7 downto 1) & DoneLed; |
oLedBank <= LedBank; |
|
Reg : process (iClk) is |
begin |
164,8 → 164,7
ADR_O => iAdr, |
DAT_O => iDat, |
SEL_O => iSel, |
ERR_O => ErrorLed, |
DON_O => DoneLed |
LEDBANK_O => LedBank2 |
); |
|
end architecture Rtl; |
/trunk/src/grpSd/unitSdController/src/SdController-Rtl-a.vhdl
56,6 → 56,7
ToSdWbSlave : aSdControllerToSdWbSlave; |
HighSpeed : std_ulogic; |
OperationBlock : aOperationBlock; |
LedBank : std_ulogic_vector(7 downto 0); |
end record aSdControllerReg; |
|
constant cDefaultSdControllerReg : aSdControllerReg := ( |
74,16 → 75,18
ToDataRam => cDefaultSdControllerToRam, |
ToSdWbSlave => cDefaultSdControllerToSdWbSlave, |
HighSpeed => cInactivated, |
OperationBlock => cDefaultOperationBlock); |
OperationBlock => cDefaultOperationBlock, |
LedBank => (others => '0')); |
|
signal R, NextR : aSdControllerReg; |
|
constant cReadTimeoutNat : natural := gClkFrequency / (1 sec / gReadTimeout) - 1; |
constant cWriteTimeoutNat : natural := gClkFrequency / (1 sec / gWriteTimeout) - 1; |
constant cNcrTimeoutNatLow : natural := gClkFrequency / (1 sec / (1 sec / 25E6 * 8)) - 1; |
constant cNcrTimeoutNatHigh : natural := gClkFrequency / (1 sec / (1 sec / 50E6 * 8)) - 1; |
constant cStartupTimeoutNat : natural := gClkFrequency / (1 sec / gStartupTimeout) - 1; |
|
constant cMaxTimeoutBitWidth : natural := LogDualis(cReadTimeoutNat); |
constant cMaxTimeoutBitWidth : natural := LogDualis(cWriteTimeoutNat); |
subtype aTimeoutValue is unsigned(cMaxTimeoutBitWidth - 1 downto 0); |
|
constant cNcrTimeoutLow : aTimeoutValue := to_unsigned(cNcrTimeoutNatLow, aTimeoutValue'length); |
90,6 → 93,7
constant cNcrTimeoutHigh : aTimeoutValue := to_unsigned(cNcrTimeoutNatHigh, aTimeoutValue'length); |
constant cStartupTimeout : aTimeoutValue := to_unsigned(cStartupTimeoutNat, aTimeoutValue'length); |
constant cReadTimeout : aTimeoutValue := to_unsigned(cReadTimeoutNat, aTimeoutValue'length); |
constant cWriteTimeout : aTimeoutValue := to_unsigned(cWriteTimeoutNat, aTimeoutValue'length); |
|
signal TimeoutEnable : std_ulogic; |
signal TimeoutDisable : std_ulogic; |
102,6 → 106,7
oSdData <= R.ToSdData; |
oSdWbSlave <= R.ToSdWbSlave; |
oHighSpeed <= R.HighSpeed; |
oLedBank <= R.LedBank; |
|
Regs : process (iClk, iRstSync) |
begin |
143,19 → 148,6
NextCmdRegion := R.CmdRegion; |
NextState := R.State; |
|
-- Status |
oLedBank <= (others => cInactivated); |
if (R.ToSdData.Mode = wide) then |
oLedBank(5) <= cActivated; |
else |
oLedBank(5) <= cInactivated; |
end if; |
if (R.HighSpeed = cActivated) then |
oLedBank(4) <= cActivated; |
else |
oLedBank(4) <= cInactivated; |
end if; |
|
case R.State is |
when startup => |
TimeoutEnable <= cActivated; |
219,8 → 211,6
|
when ACMD41 => |
if (R.SendCMD55 = cInactivated) then |
oLedBank(2) <= cActivated; |
|
case R.Region is |
when send => |
ocr.nBusy := '0'; |
258,7 → 248,6
NextCmdRegion := CMD2; |
NextRegion := send; |
|
|
when others => |
report "SdController: Unhandled state" severity error; |
end case; |
324,9 → 313,7
report "SdController: Unhandled CmdRegion" severity error; |
end case; |
|
when config => |
oLedBank(3) <= cActivated; |
|
when config => |
case R.CmdRegion is |
when SelectCard => |
case R.Region is |
433,8 → 420,9
NextR.State <= invalidCard; |
end if; |
|
when waitstate => |
when waitstate => |
NextR.ToSdData.Mode <= wide; |
-- NextR.LedBank(4) <= cActivated; |
|
if gHighSpeedMode = true then |
|
525,6 → 513,7
NextR.HighSpeed <= cActivated; |
NextRegion := send; |
NextCmdRegion := GetStatus; |
--NextR.LedBank(5)<= cActivated; |
else |
NextRegion := idle; |
NextState := requestnewoperation; |
576,10 → 565,10
|
when read => |
NextR.ToSdData.DataMode <= usual; |
oLedBank(0) <= cActivated; |
|
case R.Region is |
when send => |
NextR.LedBank(0) <= cActivated; |
-- send a read command |
NextR.ToSdCmd.Content.id <= cSdCmdReadSingleBlock; |
|
598,6 → 587,8
NextRegion := response; |
|
when response => |
NextR.LedBank(1) <= cActivated; |
|
-- wait for the response and handle it |
if (iSdCmd.Valid = cActivated) then |
if (iSdCmd.Content.id = cSdCmdReadSingleBlock) then |
612,10 → 603,12
end if; |
|
when receivedata => |
NextR.LedBank(2) <= cActivated; |
|
when waitstatedata => |
NextR.Region <= idle; |
NextR.State <= requestnewoperation; |
NextR.LedBank(3) <= cActivated; |
NextRegion := idle; |
NextState := requestnewoperation; |
|
when others => |
report "Unhandled region"; |
623,7 → 616,6
|
when write => |
NextR.ToSdData.DataMode <= usual; |
oLedBank(1) <= cActivated; |
|
case R.Region is |
when send => |
657,16 → 649,12
elsif (Timeout = cActivated) then |
NextR.State <= invalidCard; |
end if; |
|
|
when senddata => |
NextRegion := checkbusy; |
|
when checkbusy => |
null; |
when checkbusy => null; |
|
when receivedata => |
NextRegion := waitstatedata; |
|
when waitstatedata => |
NextRegion := idle; |
NextState := requestnewoperation; |
676,13 → 664,13
end case; |
|
when requestnewoperation => |
|
NextR.LedBank <= (others => '0'); |
NextR.ToSdData.DisableRb <= cInactivated; |
NextR.ToSdWbSlave.ReqOperation <= not R.ToSdWbSlave.ReqOperation; |
NextR.State <= idle; |
|
when idle => |
oLedBank(6) <= cActivated; |
NextR.LedBank(6) <= cActivated; |
|
-- wait for next operation |
if (iSdWbSlave.AckOperation = cActivated) then |
707,10 → 695,11
report "Unknown operation" severity error; |
end case; |
|
NextR.LedBank(6) <= cInactivated; |
end if; |
|
when invalidCard => |
oLedBank(7) <= cActivated; |
NextR.LedBank(7) <= cActivated; |
|
when others => |
report "SdController: Unhandled state" severity error; |
735,7 → 724,7
end if; |
|
when response => |
oLedBank(0) <= cActivated; |
-- oLedBank(0) <= cActivated; |
TimeoutEnable <= cActivated; |
TimeoutMax <= cReadTimeout; |
|
789,10 → 778,13
|
when checkbusy => |
NextR.ToSdData.CheckBusy <= cActivated; |
TimeoutEnable <= cActivated; |
TimeoutMax <= cWriteTimeout; |
|
if (iSdData.Busy = cActivated) then |
NextR.Region <= receivedata; |
if (iSdData.Valid = cActivated) then |
NextR.Region <= waitstatedata; |
NextR.ToSdData.CheckBusy <= cInactivated; |
TimeoutDisable <= cActivated; |
end if; |
|
when receivedata => |
809,6 → 801,7
|
elsif (Timeout = cActivated) then |
NextR.State <= invalidCard; |
NextR.LedBank(5) <= cActivated; |
end if; |
|
|
/trunk/src/grpSd/unitSdController/src/SdController-e.vhdl
37,7 → 37,8
gClkFrequency : natural := 25E6; |
gHighSpeedMode : boolean := true; |
gStartupTimeout : time := 1 ms; |
gReadTimeout : time := 100 ms |
gReadTimeout : time := 100 ms; |
gWriteTimeout : time := 250 ms |
); |
port ( |
iClk : in std_ulogic; -- rising edge |