URL
https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk
Subversion Repositories sdhc-sc-core
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/sdhc-sc-core
- from Rev 168 to Rev 169
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Rev 168 → Rev 169
/trunk/src/grpSd/unitTbdSd/syn/TbdSdSyn.sdc
0,0 → 1,109
## Generated SDC file "TbdSdSyn.sdc" |
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## Copyright (C) 1991-2010 Altera Corporation |
## Your use of Altera Corporation's design tools, logic functions |
## and other software and tools, and its AMPP partner logic |
## functions, and any output files from any of the foregoing |
## (including device programming or simulation files), and any |
## associated documentation or information are expressly subject |
## to the terms and conditions of the Altera Program License |
## Subscription Agreement, Altera MegaCore Function License |
## Agreement, or other applicable license agreement, including, |
## without limitation, that your use is for the sole purpose of |
## programming logic devices manufactured by Altera and sold by |
## Altera or its authorized distributors. Please refer to the |
## applicable agreement for further details. |
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## VENDOR "Altera" |
## PROGRAM "Quartus II" |
## VERSION "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition" |
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## DATE "Thu Oct 21 20:31:30 2010" |
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## |
## DEVICE "EP2C35F484C8" |
## |
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#************************************************************** |
# Time Information |
#************************************************************** |
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set_time_format -unit ns -decimal_places 3 |
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#************************************************************** |
# Create Clock |
#************************************************************** |
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create_clock -name {iClk} -period 10.000 -waveform { 0.000 5.000 } [get_ports {iClk}] |
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#************************************************************** |
# Create Generated Clock |
#************************************************************** |
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#************************************************************** |
# Set Clock Latency |
#************************************************************** |
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#************************************************************** |
# Set Clock Uncertainty |
#************************************************************** |
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#************************************************************** |
# Set Input Delay |
#************************************************************** |
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#************************************************************** |
# Set Output Delay |
#************************************************************** |
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#************************************************************** |
# Set Clock Groups |
#************************************************************** |
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#************************************************************** |
# Set False Path |
#************************************************************** |
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set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_b09:dffpipe20|dffe21a*}] |
set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_a09:dffpipe17|dffe18a*}] |
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#************************************************************** |
# Set Multicycle Path |
#************************************************************** |
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#************************************************************** |
# Set Maximum Delay |
#************************************************************** |
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#************************************************************** |
# Set Minimum Delay |
#************************************************************** |
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#************************************************************** |
# Set Input Transition |
#************************************************************** |
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trunk/src/grpSd/unitTbdSd/syn/TbdSdSyn.sdc
Property changes :
Added: svn:executable
## -0,0 +1 ##
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