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URL https://opencores.org/ocsvn/sdhc-sc-core/sdhc-sc-core/trunk

Subversion Repositories sdhc-sc-core

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    /sdhc-sc-core
    from Rev 179 to Rev 180
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Rev 179 → Rev 180

/trunk/src/grpSd/unitSdTop/src/SdTop-Rtl-ea.vhdl
82,26 → 82,25
 
architecture Rtl of SdTop is
 
signal iSdWbSync, oSdControllerSync : aSdWbSlaveToSdController;
signal iSdControllerSync, oSdWbSync : aSdControllerToSdWbSlave;
signal iWbCtrl : aWbSlaveCtrlInput;
signal oWbCtrl : aWbSlaveCtrlOutput;
signal iWbDat : aSdWbSlaveDataInput;
signal oWbDat : aSdWbSlaveDataOutput;
signal SdWbSlaveToWriteFifo : aoWriteFifo;
signal SdWbSlaveToReadFifo : aoReadFifo;
signal WriteFifoToSdWbSlave : aiWriteFifo;
signal SdWbSlaveFromReadFifo : aiReadFifo;
signal ReadFifoQTemp : std_logic_vector(31 downto 0);
signal WriteFifoQTemp : std_logic_vector(31 downto 0);
signal iReadWriteFifo : aiReadFifo;
signal oReadWriteFifo : aoReadFifo;
signal iWriteReadFifo : aiWriteFifo;
signal oWriteReadFifo : aoWriteFifo;
signal iSdCtrl, oWbCtrl : aSdWbSlaveToSdController;
signal oSdCtrl, iWbCtrl : aSdControllerToSdWbSlave;
signal iSdWriteFifo : aiReadFifo;
signal oSdWriteFifo : aoReadFifo;
signal iSdReadFifo : aiWriteFifo;
signal oSdReadFifo : aoWriteFifo;
signal iWbWriteFifo : aiWriteFifo;
signal oWbWriteFifo : aoWriteFifo;
signal iWbReadFifo : aiReadFifo;
signal oWbReadFifo : aoReadFifo;
 
signal ReadFifoQTemp : std_logic_vector(31 downto 0);
signal WriteFifoQTemp : std_logic_vector(31 downto 0);
 
begin
 
--------------------------------------------------------------------------------
-- clk domains
--------------------------------------------------------------------------------
SdClkDomain_inst: entity work.SdClkDomain
generic map (
gClkFrequency => gClkFrequency,
114,35 → 113,43
oSclk => oSclk,
ioData => ioData,
oLedBank => oLedBank,
oSdCtrl => iSdControllerSync,
iSdCtrl => oSdControllerSync,
iSdWriteFifo => iReadWriteFifo,
oSdWriteFifo => oReadWriteFifo,
iSdReadFifo => iWriteReadFifo,
oSdReadFifo => oWriteReadFifo
oSdCtrl => oSdCtrl,
iSdCtrl => iSdCtrl,
iSdWriteFifo => iSdWriteFifo,
oSdWriteFifo => oSdWriteFifo,
iSdReadFifo => iSdReadFifo,
oSdReadFifo => oSdReadFifo
);
 
-- map wishbone signals to internal signals
iWbCtrl <= (
Cyc => iCyc,
Lock => iLock,
Stb => iStb,
We => iWe,
Cti => iCti,
Bte => iBte
);
WbClkDomain_inst: entity work.WbClkDomain
port map (
iWbClk => iWbClk,
iWbRstSync => iWbRstSync,
iCyc => iCyc,
iLock => iLock,
iStb => iStb,
iWe => iWe,
iCti => iCti,
iBte => iBte,
iSel => iSel,
iAdr => iAdr,
iDat => iDat,
oDat => oDat,
oAck => oAck,
oErr => oErr,
oRty => oRty,
iWriteFifo => iWbWriteFifo,
iReadFifo => iWbReadFifo,
oWriteFifo => oWbWriteFifo,
oReadFifo => oWbReadFifo,
oWbToSdCtrl => oWbCtrl,
iSdCtrlToWb => iWbCtrl
);
 
oAck <= oWbCtrl.Ack;
oErr <= oWbCtrl.Err;
oRty <= oWbCtrl.Rty;
oDat <= oWbDat.Dat;
 
iWbDat <= (
Sel => iSel,
Adr => iAdr,
Dat => iDat
);
 
--------------------------------------------------------------------------------
-- clk domain synchronization
--------------------------------------------------------------------------------
SdWbControllerSync_inst: entity work.SdWbControllerSync
generic map (
gUseSameClocks => gUseSameClocks
152,63 → 159,37
iWbRstSync => iWbRstSync,
iSdClk => iSdClk,
iSdRstSync => iSdRstSync,
iSdWb => iSdWbSync,
oSdWb => oSdWbSync,
iSdController => iSdControllerSync,
oSdController => oSdControllerSync
iSdWb => oWbCtrl,
oSdWb => iWbCtrl,
iSdController => oSdCtrl,
oSdController => iSdCtrl
);
 
SdWbSlave_inst : entity work.SdWbSlave
port map (
iClk => iWbClk,
iRstSync => iWbRstSync,
 
-- wishbone
iWbCtrl => iWbCtrl,
oWbCtrl => oWbCtrl,
iWbDat => iWbDat,
oWbDat => oWbDat,
 
-- To sd controller
iController => oSdWbSync,
oController => iSdWbSync,
 
-- To write fifo
oWriteFifo => SdWbSlaveToWriteFifo,
iWriteFifo => WriteFifoToSdWbSlave,
 
-- To read fifo
oReadFifo => SdWbSlaveToReadFifo,
iReadFifo => SdWbSlaveFromReadFifo
);
 
WriteDataFifo_inst: entity work.WriteDataFifo
port map (
data => std_logic_vector(SdWbSlaveToWriteFifo.data),
data => std_logic_vector(oWbWriteFifo.data),
rdclk => iSdClk,
rdreq => oReadWriteFifo.rdreq,
rdreq => oSdWriteFifo.rdreq,
wrclk => iWbClk,
wrreq => SdWbSlaveToWriteFifo.wrreq,
wrreq => oWbWriteFifo.wrreq,
q => ReadFifoQTemp,
rdempty => iReadWriteFifo.rdempty,
wrfull => WriteFifoToSdWbSlave.wrfull
rdempty => iSdWriteFifo.rdempty,
wrfull => iWbWriteFifo.wrfull
);
iSdWriteFifo.q <= std_ulogic_vector(ReadFifoQTemp);
 
iReadWriteFifo.q <= std_ulogic_vector(ReadFifoQTemp);
 
ReadDataFifo_inst: entity work.WriteDataFifo
port map (
data => std_logic_vector(oWriteReadFifo.data),
data => std_logic_vector(oSdReadFifo.data),
rdclk => iWbClk,
rdreq => SdWbSlaveToReadFifo.rdreq,
rdreq => oWbReadFifo.rdreq,
wrclk => iSdClk,
wrreq => oWriteReadFifo.wrreq,
wrreq => oSdReadFifo.wrreq,
q => WriteFifoQTemp,
rdempty => SdWbSlaveFromReadFifo.rdempty,
wrfull => iWriteReadFifo.wrfull
rdempty => iWbReadFifo.rdempty,
wrfull => iSdReadFifo.wrfull
);
iWbReadFifo.q <= std_ulogic_vector(WriteFifoQTemp);
 
SdWbSlaveFromReadFifo.q <= std_ulogic_vector(WriteFifoQTemp);
 
end architecture Rtl;
 
/trunk/src/grpSd/unitWbClkDomain/src/WbClkDomain-Rtl-ea.vhdl
0,0 → 1,126
-- SDHC-SC-Core
-- Secure Digital High Capacity Self Configuring Core
--
-- (C) Copyright 2010, Rainer Kastl
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions are met:
-- * Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- * Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
-- * Neither the name of the <organization> nor the
-- names of its contributors may be used to endorse or promote products
-- derived from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-- ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-- DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-- SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-- File : WbClkDomain-Rtl-ea.vhdl
-- Owner : Rainer Kastl
-- Description : Top level of wishbone clock domain
-- Links :
--
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.Global.all;
use work.Wishbone.all;
use work.Sd.all;
use work.SdWb.all;
 
entity WbClkDomain is
port (
iWbClk : in std_ulogic;
iWbRstSync : in std_ulogic;
iCyc : in std_ulogic;
iLock : in std_ulogic;
iStb : in std_ulogic;
iWe : in std_ulogic;
iCti : in std_ulogic_vector(2 downto 0);
iBte : in std_ulogic_vector(1 downto 0);
iSel : in std_ulogic_vector(0 downto 0);
iAdr : in std_ulogic_vector(6 downto 4);
iDat : in std_ulogic_vector(31 downto 0);
oDat : out std_ulogic_vector(31 downto 0);
oAck : out std_ulogic;
oErr : out std_ulogic;
oRty : out std_ulogic;
iWriteFifo : in aiWriteFifo;
iReadFifo : in aiReadFifo;
oWriteFifo : out aoWriteFifo;
oReadFifo : out aoReadFifo;
oWbToSdCtrl : out aSdWbSlaveToSdController;
iSdCtrlToWb : in aSdControllerToSdWbSlave
);
 
end entity WbClkDomain;
 
architecture Rtl of WbClkDomain is
 
signal iWbCtrl : aWbSlaveCtrlInput;
signal oWbCtrl : aWbSlaveCtrlOutput;
signal iWbDat : aSdWbSlaveDataInput;
signal oWbDat : aSdWbSlaveDataOutput;
begin
 
SdWbSlave_inst : entity work.SdWbSlave
port map (
iClk => iWbClk,
iRstSync => iWbRstSync,
 
-- wishbone
iWbCtrl => iWbCtrl,
oWbCtrl => oWbCtrl,
iWbDat => iWbDat,
oWbDat => oWbDat,
 
-- To sd controller
iController => iSdCtrlToWb,
oController => oWbToSdCtrl,
 
-- To write fifo
oWriteFifo => oWriteFifo,
iWriteFifo => iWriteFifo,
 
-- To read fifo
oReadFifo => oReadFifo,
iReadFifo => iReadFifo
);
 
-- map wishbone signals to internal signals
iWbCtrl <= (
Cyc => iCyc,
Lock => iLock,
Stb => iStb,
We => iWe,
Cti => iCti,
Bte => iBte
);
 
oAck <= oWbCtrl.Ack;
oErr <= oWbCtrl.Err;
oRty <= oWbCtrl.Rty;
oDat <= oWbDat.Dat;
 
iWbDat <= (
Sel => iSel,
Adr => iAdr,
Dat => iDat
);
 
 
end architecture Rtl;
 
/trunk/src/grpSd/unitSdVerificationTestbench/Files.tcl
60,6 → 60,7
Sd SdWbSdControllerSync {Rtl}
Cyclone2 WriteDataFifo {Syn}
Sd SdClkDomain {Rtl}
Sd WbClkDomain {Rtl}
Sd SdTop {Rtl}}
 
set svunits {Sd SdCardModel

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