URL
https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk
Subversion Repositories sdr_ctrl
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- This comparison shows the changes necessary to convert path
/sdr_ctrl/trunk/rtl/top
- from Rev 33 to Rev 37
- ↔ Reverse comparison
Rev 33 → Rev 37
/sdrc_top.v
23,10 → 23,12
nothing |
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Author(s): Dinesh Annayya, dinesha@opencores.org |
Version : 1.0 - 8th Jan 2012 |
Version : 0.0 - 8th Jan 2012 |
Initial version with 16/32 Bit SDRAM Support |
: 1.1 - 24th Jan 2012 |
: 0.1 - 24th Jan 2012 |
8 Bit SDRAM Support is added |
0.2 - 31st Jan 2012 |
sdram_dq and sdram_pad_clk are internally generated |
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Copyright (C) 2000 Authors and OPENCORES.ORG |
55,7 → 57,7
*******************************************************************/ |
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`include "sdrc.def" |
`include "sdrc_define.v" |
module sdrc_top |
( |
sdr_width , |
78,7 → 80,6
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/* Interface to SDRAMs */ |
sdram_clk , |
sdram_pad_clk , |
sdram_resetn , |
sdr_cs_n , |
sdr_cke , |
88,9 → 89,7
sdr_dqm , |
sdr_ba , |
sdr_addr , |
pad_sdr_din , |
sdr_dout , |
sdr_den_n , |
sdr_dq , |
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/* Parameters */ |
sdr_init_done , |
123,7 → 122,6
// Global Variable |
// ---------------------------------------------- |
input sdram_clk ; // SDRAM Clock |
input sdram_pad_clk ; // SDRAM Clock from Pad, used for registering Read Data |
input sdram_resetn ; // Reset Signal |
input [1:0] sdr_width ; // 2'b00 - 32 Bit SDR, 2'b01 - 16 Bit SDR, 2'b1x - 8 Bit |
input [1:0] cfg_colbits ; // 2'b00 - 8 Bit column address, |
156,9 → 154,7
output [SDR_BW-1:0] sdr_dqm ; // SDRAM Data Mask |
output [1:0] sdr_ba ; // SDRAM Bank Enable |
output [11:0] sdr_addr ; // SDRAM Address |
input [SDR_DW-1:0] pad_sdr_din ; // SDRA Data Input |
output [SDR_DW-1:0] sdr_dout ; // SDRAM Data Output |
output [SDR_BW-1:0] sdr_den_n ; // SDRAM Data Output enable |
inout [SDR_DW-1:0] sdr_dq ; // SDRA Data Input/output |
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//------------------------------------------------ |
// Configuration Parameter |
192,6 → 188,22
wire [dw-1:0] app_wr_data ; // sdr write data |
wire [dw-1:0] app_rd_data ; // sdr read data |
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/**************************************** |
* These logic has to be implemented using Pads |
* **************************************/ |
wire [SDR_DW-1:0] pad_sdr_din ; // SDRA Data Input |
wire [SDR_DW-1:0] sdr_dout ; // SDRAM Data Output |
wire [SDR_BW-1:0] sdr_den_n ; // SDRAM Data Output enable |
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assign sdr_dq = (&sdr_den_n == 1'b0) ? sdr_dout : {SDR_DW{1'bz}}; |
assign pad_sdr_din = sdr_dq; |
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// sdram pad clock is routed back through pad |
// SDRAM Clock from Pad, used for registering Read Data |
wire #(1.0) sdram_pad_clk = sdram_clk; |
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/************** Ends Here **************************/ |
wb2sdrc u_wb2sdrc ( |
// WB bus |
.wb_rst_i (wb_rst_i ) , |