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https://opencores.org/ocsvn/sdr_ctrl/sdr_ctrl/trunk
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/sdr_ctrl/trunk
- from Rev 49 to Rev 50
- ↔ Reverse comparison
Rev 49 → Rev 50
/rtl/core/sdrc_bank_fsm.v
93,10 → 93,10
parameter APP_AW = 30; // Application Address Width |
parameter APP_DW = 32; // Application Data Width |
parameter APP_BW = 4; // Application Byte Width |
parameter APP_RW = 9; // Application Request Width |
|
parameter SDR_DW = 16; // SDR Data Width |
parameter SDR_BW = 2; // SDR Byte Width |
parameter REQ_BW = 12; // Request Width |
input clk, reset_n; |
|
/* Req from bank_ctl */ |
105,7 → 105,7
input [`SDR_REQ_ID_W-1:0] r2b_req_id; |
input [11:0] r2b_raddr; |
input [11:0] r2b_caddr; |
input [APP_RW-1:0] r2b_len; |
input [REQ_BW-1:0] r2b_len; |
output b2r_ack; |
input sdr_dma_last; |
|
114,7 → 114,7
tras_ok, b2x_wrap; |
output [`SDR_REQ_ID_W-1:0] b2x_id; |
output [11:0] b2x_addr; |
output [APP_RW-1:0] b2x_len; |
output [REQ_BW-1:0] b2x_len; |
output [1:0] b2x_cmd; |
input x2b_ack; |
|
142,8 → 142,8
wire [`SDR_REQ_ID_W-1:0] b2x_id; |
reg [`SDR_REQ_ID_W-1:0] l_id; |
reg [11:0] b2x_addr; |
reg [APP_RW-1:0] l_len; |
wire [APP_RW-1:0] b2x_len; |
reg [REQ_BW-1:0] l_len; |
wire [REQ_BW-1:0] b2x_len; |
reg [1:0] b2x_cmd; |
reg bank_valid; |
reg [11:0] bank_row; |
170,7 → 170,6
else begin |
|
bank_valid <= (x2b_refresh || bank_prech_page_closed) ? 1'b0 : // force the bank status to be invalid |
// bank_valid <= (x2b_refresh) ? 1'b0 : |
(activate_bank) ? 1'b1 : bank_valid; |
|
tras_cntr <= (activate_bank) ? tras_delay : |
/rtl/core/sdrc_req_gen.v
34,7 → 34,10
This module takes requests from the memory controller, |
chops them to page boundaries if wrap=0, |
and passes the request to bank_ctl |
|
|
Note: With Wrap = 0, each request from Application layer will be splited into two request, |
if the current burst cross the page boundary. |
|
To Do: |
nothing |
|
112,6 → 115,7
parameter SDR_DW = 16; // SDR Data Width |
parameter SDR_BW = 2; // SDR Byte Width |
|
parameter REQ_BW = 12; // Request Width |
input clk ; |
input reset_n ; |
input [1:0] cfg_colbits ; // 2'b00 - 8 Bit column address, 2'b01 - 9 Bit, 10 - 10 bit, 11 - 11Bits |
126,19 → 130,19
output req_ack ; // Request Ack |
|
/* Req to bank_ctl */ |
output r2x_idle ; |
output r2b_req ; |
output r2b_start ; |
output r2b_last ; |
output r2b_write ; |
output r2b_wrap ; |
output r2x_idle ; |
output r2b_req ; // Request |
output r2b_start ; // First Junk of the Burst Access |
output r2b_last ; // Last Junk of the Burst Access |
output r2b_write ; // 1 - Write, 0 - Read |
output r2b_wrap ; // 1 - Wrap the Address at the page boundary. |
output [`SDR_REQ_ID_W-1:0] r2b_req_id; |
output [1:0] r2b_ba ; |
output [11:0] r2b_raddr ; |
output [11:0] r2b_caddr ; |
output [APP_RW-1:0] r2b_len ; |
input b2r_ack ; |
input b2r_arb_ok ; |
output [1:0] r2b_ba ; // Bank Address |
output [11:0] r2b_raddr ; // Row Address |
output [11:0] r2b_caddr ; // Column Address |
output [REQ_BW-1:0] r2b_len ; // Burst Length |
input b2r_ack ; // Request Ack |
input b2r_arb_ok ; // Bank controller fifo is not full and ready to accept the command |
// |
input [1:0] sdr_width; // 2'b00 - 32 Bit, 2'b01 - 16 Bit, 2'b1x - 8Bit |
|
153,11 → 157,11
reg r2x_idle, req_ack, r2b_req, r2b_start, |
r2b_write, req_idle, req_ld, lcl_wrap; |
reg [`SDR_REQ_ID_W-1:0] r2b_req_id; |
reg [APP_RW-1:0] lcl_req_len; |
reg [REQ_BW-1:0] lcl_req_len; |
|
wire r2b_last, page_ovflw; |
wire [APP_RW-1:0] r2b_len, next_req_len; |
wire [APP_RW:0] max_r2b_len; |
wire [REQ_BW-1:0] r2b_len, next_req_len; |
wire [REQ_BW:0] max_r2b_len; |
|
reg [1:0] r2b_ba; |
reg [11:0] r2b_raddr; |
211,6 → 215,8
// The wrapping functionality will be handle by the bank control module and |
// column address will rewind back as follows XX -> FF ? 00 ? 1 |
// |
// Note: With Wrap = 0, each request from Application layer will be spilited into two request, |
// if the current burst cross the page boundary. |
assign page_ovflw = ({1'b0, lcl_req_len} > max_r2b_len) ? ~lcl_wrap : 1'b0; |
|
assign r2b_len = (page_ovflw) ? max_r2b_len : lcl_req_len; |
290,8 → 296,8
always @ (posedge clk) begin |
// Bank Bits are always - 2 Bits |
r2b_ba <= (cfg_colbits == 2'b00) ? {map_address[9:8]} : |
(cfg_colbits == 2'b01) ? {map_address[10:9]} : |
(cfg_colbits == 2'b10) ? {map_address[11:10]} : map_address[12:11]; |
(cfg_colbits == 2'b01) ? {map_address[10:9]} : |
(cfg_colbits == 2'b10) ? {map_address[11:10]} : map_address[12:11]; |
|
/******************** |
* Colbits Mapping: |
301,12 → 307,12
* 2'b11 - 11 Bits |
************************/ |
r2b_caddr <= (cfg_colbits == 2'b00) ? {4'b0, map_address[7:0]} : |
(cfg_colbits == 2'b01) ? {3'b0, map_address[8:0]} : |
(cfg_colbits == 2'b10) ? {2'b0, map_address[9:0]} : {1'b0, map_address[10:0]}; |
(cfg_colbits == 2'b01) ? {3'b0, map_address[8:0]} : |
(cfg_colbits == 2'b10) ? {2'b0, map_address[9:0]} : {1'b0, map_address[10:0]}; |
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r2b_raddr <= (cfg_colbits == 2'b00) ? map_address[21:10] : |
(cfg_colbits == 2'b01) ? map_address[22:11] : |
(cfg_colbits == 2'b10) ? map_address[23:12] : map_address[24:13]; |
(cfg_colbits == 2'b01) ? map_address[22:11] : |
(cfg_colbits == 2'b10) ? map_address[23:12] : map_address[24:13]; |
end |
|
endmodule // sdr_req_gen |
/rtl/core/sdrc_xfr_ctl.v
132,10 → 132,10
parameter APP_AW = 30; // Application Address Width |
parameter APP_DW = 32; // Application Data Width |
parameter APP_BW = 4; // Application Byte Width |
parameter APP_RW = 9; // Application Request Width |
|
parameter SDR_DW = 16; // SDR Data Width |
parameter SDR_BW = 2; // SDR Byte Width |
parameter REQ_BW = 12; // Request Width |
|
|
input clk, reset_n; |
146,7 → 146,7
input [`SDR_REQ_ID_W-1:0] b2x_id; |
input [1:0] b2x_ba; |
input [11:0] b2x_addr; |
input [APP_RW-1:0] b2x_len; |
input [REQ_BW-1:0] b2x_len; |
input [1:0] b2x_cmd; |
output x2b_ack; |
|
201,8 → 201,8
wire [1:0] xfr_ba; |
reg [1:0] l_ba; |
wire [11:0] xfr_addr; |
wire [APP_RW-1:0] xfr_len, next_xfr_len; |
reg [APP_RW-1:0] l_len; |
wire [REQ_BW-1:0] xfr_len, next_xfr_len; |
reg [REQ_BW-1:0] l_len; |
|
reg mgmt_idle, mgmt_req; |
reg [3:0] mgmt_cmd; |
279,11 → 279,11
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assign wr_start = ld_xfr & b2x_write & b2x_start; |
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assign rd_last = rd_next & last_burst & ~|xfr_len[APP_RW-1:1]; |
assign rd_last = rd_next & last_burst & ~|xfr_len[REQ_BW-1:1]; |
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//assign wr_last = wr_next & last_burst & ~|xfr_len[APP_RW-1:1]; |
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assign wr_last = last_burst & ~|xfr_len[APP_RW-1:1]; |
assign wr_last = last_burst & ~|xfr_len[REQ_BW-1:1]; |
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//assign xfr_ba = (ld_xfr) ? b2x_ba : l_ba; |
assign xfr_ba = (sel_mgmt) ? mgmt_ba : |
/rtl/core/sdrc_bs_convert.v
79,7 → 79,6
parameter APP_AW = 30; // Application Address Width |
parameter APP_DW = 32; // Application Data Width |
parameter APP_BW = 4; // Application Byte Width |
parameter APP_RW = 9; // Application Request Width |
|
parameter SDR_DW = 16; // SDR Data Width |
parameter SDR_BW = 2; // SDR Byte Width |
/rtl/core/sdrc_core.v
39,7 → 39,10
: 0.1 - 24th Jan 2012 |
8 Bit SDRAM Support is added |
0.2 - 2nd Feb 2012 |
Improved the command pipe structure to accept up-to 4 command of different bank. |
Improved the command pipe structure to accept up-to |
4 command of different bank. |
0.3 - 7th Feb 2012 |
Bug fix for parameter defination for request length has changed from 9 to 12 |
|
|
Copyright (C) 2000 Authors and OPENCORES.ORG |
130,6 → 133,7
parameter SDR_DW = 16; // SDR Data Width |
parameter SDR_BW = 2; // SDR Byte Width |
|
parameter REQ_BW = 12; // Request Width |
|
//----------------------------------------------- |
// Global Variable |
199,13 → 203,13
wire [1:0] r2b_ba; |
wire [11:0] r2b_raddr; |
wire [11:0] r2b_caddr; |
wire [APP_RW-1:0] r2b_len; |
wire [REQ_BW-1:0] r2b_len; |
|
// SDR BANK CTL |
wire [`SDR_REQ_ID_W-1:0]b2x_id; |
wire [1:0] b2x_ba; |
wire [11:0] b2x_addr; |
wire [APP_RW-1:0] b2x_len; |
wire [REQ_BW-1:0] b2x_len; |
wire [1:0] b2x_cmd; |
|
// SDR_XFR_CTL |
/rtl/core/sdrc_bank_ctl.v
97,10 → 97,10
parameter APP_AW = 30; // Application Address Width |
parameter APP_DW = 32; // Application Data Width |
parameter APP_BW = 4; // Application Byte Width |
parameter APP_RW = 9; // Application Request Width |
|
parameter SDR_DW = 16; // SDR Data Width |
parameter SDR_BW = 2; // SDR Byte Width |
parameter REQ_BW = 12; // Request Width |
input clk, reset_n; |
|
input [1:0] a2b_req_depth; |
112,7 → 112,7
input [1:0] r2b_ba; |
input [11:0] r2b_raddr; |
input [11:0] r2b_caddr; |
input [APP_RW-1:0] r2b_len; |
input [REQ_BW-1:0] r2b_len; |
output b2r_arb_ok, b2r_ack; |
input sdr_req_norm_dma_last; |
|
122,7 → 122,7
output [`SDR_REQ_ID_W-1:0] b2x_id; |
output [1:0] b2x_ba; |
output [11:0] b2x_addr; |
output [APP_RW-1:0] b2x_len; |
output [REQ_BW-1:0] b2x_len; |
output [1:0] b2x_cmd; |
input x2b_ack; |
|
141,7 → 141,7
wire [3:0] r2i_req, i2r_ack, i2x_req, |
i2x_start, i2x_last, i2x_wrap, tras_ok; |
wire [11:0] i2x_addr0, i2x_addr1, i2x_addr2, i2x_addr3; |
wire [APP_RW-1:0] i2x_len0, i2x_len1, i2x_len2, i2x_len3; |
wire [REQ_BW-1:0] i2x_len0, i2x_len1, i2x_len2, i2x_len3; |
wire [1:0] i2x_cmd0, i2x_cmd1, i2x_cmd2, i2x_cmd3; |
wire [`SDR_REQ_ID_W-1:0] i2x_id0, i2x_id1, i2x_id2, i2x_id3; |
|
149,7 → 149,7
wire b2x_idle, b2x_start, b2x_last, b2x_wrap; |
wire [`SDR_REQ_ID_W-1:0] b2x_id; |
wire [11:0] b2x_addr; |
wire [APP_RW-1:0] b2x_len; |
wire [REQ_BW-1:0] b2x_len; |
wire [1:0] b2x_cmd; |
wire [3:0] x2i_ack; |
reg [1:0] b2x_ba; |