URL
https://opencores.org/ocsvn/sdram_controller/sdram_controller/trunk
Subversion Repositories sdram_controller
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- This comparison shows the changes necessary to convert path
/sdram_controller/trunk
- from Rev 7 to Rev 8
- ↔ Reverse comparison
Rev 7 → Rev 8
/sdram_support.vhd
114,7 → 114,7
entity sdram_dcm is |
port( |
reset : in std_logic; |
clk50mhz : in std_logic; |
clk100mhz : in std_logic; |
locked : out std_logic; |
dram_clkp : out std_logic; |
dram_clkn : out std_logic; |
127,12 → 127,6
|
architecture impl of sdram_dcm is |
|
signal dcm0_locked : std_logic; |
signal dcm0_clk_raw_000 : std_logic; |
signal dcm0_clk_000 : std_logic; |
signal dcm0_clk_fxr_000 : std_logic; |
signal dcm0_clk_fx_000 : std_logic; |
|
signal dcm1_reset : std_logic; |
signal dcm1_locked : std_logic; |
signal dcm1_clk_raw_000 : std_logic; |
143,57 → 137,8
signal dcm1_clk_270 : std_logic; |
|
begin |
|
SDRAM_DCM0 : DCM_SP |
generic map ( |
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 |
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 |
CLKFX_DIVIDE => 2, -- Can be any integer from 1 to 32 |
CLKFX_MULTIPLY => 4, -- Can be any integer from 1 to 32 |
CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature |
CLKIN_PERIOD => 20.0, -- Specify period of input clock |
CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of "NONE", "FIXED" or "VARIABLE" |
CLK_FEEDBACK => "1X", -- Specify clock feedback of "NONE", "1X" or "2X" |
DESKEW_ADJUST => "SOURCE_SYNCHRONOUS", -- "SOURCE_SYNCHRONOUS", "SYSTEM_SYNCHRONOUS" or |
-- an integer from 0 to 15 |
DLL_FREQUENCY_MODE => "LOW", -- "HIGH" or "LOW" frequency mode for DLL |
DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE |
PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255 |
STARTUP_WAIT => FALSE) -- Delay configuration DONE until DCM_SP LOCK, TRUE/FALSE |
port map ( |
CLK0 => dcm0_clk_raw_000, -- 0 degree DCM CLK ouptput |
CLK90 => open, -- 90 degree DCM CLK output |
CLK180 => open, -- 180 degree DCM CLK output |
CLK270 => open, -- 270 degree DCM CLK output |
CLK2X => open, -- 2X DCM CLK output |
CLK2X180 => open, -- 2X, 180 degree DCM CLK out |
CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE) |
CLKFX => dcm0_clk_fxr_000, -- DCM CLK synthesis out (M/D) |
CLKFX180 => open, -- 180 degree CLK synthesis out |
LOCKED => dcm0_locked, -- DCM LOCK status output (means feedback is in phase with main clock) |
PSDONE => open, -- Dynamic phase adjust done output |
STATUS => open, -- 8-bit DCM status bits output |
CLKFB => dcm0_clk_000, -- DCM clock feedback |
CLKIN => clk50mhz, -- Clock input (from IBUFG, BUFG or DCM) |
PSCLK => '0', -- Dynamic phase adjust clock input |
PSEN => '0', -- Dynamic phase adjust enable input |
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement |
RST => reset -- DCM asynchronous reset input |
); |
|
BUFG_DCM0_000 : BUFG |
port map ( |
O => dcm0_clk_000, -- Clock buffer output |
I => dcm0_clk_raw_000 -- Clock buffer input |
); |
|
BUFG_DCM0_FX_000 : BUFG |
port map ( |
O => dcm0_clk_fx_000, -- Clock buffer output |
I => dcm0_clk_fxr_000 -- Clock buffer input |
); |
|
SDRAM_DCM1 : DCM_SP |
SDRAM_DCM : DCM_SP |
generic map ( |
CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5 |
-- 7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0 |
223,7 → 168,7
PSDONE => open, -- Dynamic phase adjust done output |
STATUS => open, -- 8-bit DCM status bits output |
CLKFB => dcm1_clk_000, -- DCM clock feedback |
CLKIN => dcm0_clk_fx_000, -- Clock input (from IBUFG, BUFG or DCM) |
CLKIN => clk100mhz, -- Clock input (from IBUFG, BUFG or DCM) |
PSCLK => '0', -- Dynamic phase adjust clock input |
PSEN => '0', -- Dynamic phase adjust enable input |
PSINCDEC => '0', -- Dynamic phase adjust increment/decrement |
278,7 → 223,7
S => '0' -- 1-bit set input |
); |
|
locked <= dcm0_locked and dcm1_locked; |
locked <= dcm1_locked; |
|
clk_000 <= dcm1_clk_000; |
clk_090 <= dcm1_clk_090; |
/sdram.vhd
58,15 → 58,15
-- TODO: implement reset signal |
entity sdram_controller is |
port( -- user facing signals |
clk50mhz : in std_logic; |
en : in std_logic; |
reset : in std_logic; |
op : in std_logic_vector(1 downto 0); -- 00/11: NOP, 01: READ, 10: write |
addr : in std_logic_vector(25 downto 0); -- address to read/write |
op_ack : out std_logic; -- op, addr and data_i should be captured when this goes high |
busy_n : out std_logic; -- busy when LOW, ops will be ignored until busy goes high again |
data_o : out std_logic_vector(7 downto 0); -- data from read shows up here |
data_i : in std_logic_vector(7 downto 0); -- data to write needs to be here |
clk100mhz : in std_logic; |
en : in std_logic; |
reset : in std_logic; |
op : in std_logic_vector(1 downto 0); -- 00/11: NOP, 01: READ, 10: write |
addr : in std_logic_vector(25 downto 0); -- address to read/write |
op_ack : out std_logic; -- op, addr and data_i should be captured when this goes high |
busy_n : out std_logic; -- busy when LOW, ops will be ignored until busy goes high again |
data_o : out std_logic_vector(7 downto 0); -- data from read shows up here |
data_i : in std_logic_vector(7 downto 0); -- data to write needs to be here |
|
-- SDRAM facing signals |
dram_clkp : out std_logic; -- 0 deg phase 100mhz clock going out to SDRAM chip |
91,7 → 91,7
component sdram_dcm is |
port( |
reset : in std_logic; |
clk50mhz : in std_logic; |
clk100mhz : in std_logic; |
locked : out std_logic; |
dram_clkp : out std_logic; |
dram_clkn : out std_logic; |
291,6 → 291,11
|
signal data0_o : std_logic_vector(7 downto 0); |
signal data1_o : std_logic_vector(7 downto 0); |
|
-- |
signal cap_en : std_logic; |
signal addr_save : std_logic_vector(25 downto 0); |
signal datai_save : std_logic_vector(7 downto 0); |
|
begin |
|
298,7 → 303,7
DRAM_DCM: sdram_dcm |
port map( |
reset => reset, |
clk50mhz => clk50mhz, |
clk100mhz => clk100mhz, |
locked => dcm_locked, |
dram_clkp => dram_clkp, |
dram_clkn => dram_clkn, |
441,8 → 446,8
clk180 => clk_180, |
clk270 => clk_270, |
rst => writer_rst, |
addr => addr(0), |
data_o => data_i, |
addr => addr_save(0), |
data_o => datai_save, |
dqs => dqs_out, |
dm => dram_dm, |
dq => dq_out |
451,7 → 456,17
|
debug_reg <= x"00"; |
dram_cs <= '0'; |
data_o <= data1_o when addr(0) = '1' else data0_o; |
data_o <= data1_o when addr_save(0) = '1' else data0_o; |
|
process (clk_000) |
begin |
if (rising_edge(clk_000)) then |
if (cap_en = '1') then |
addr_save <= addr; |
datai_save <= data_i; |
end if; |
end if; |
end process; |
|
-- command state machine |
process (clk_000) |
462,7 → 477,8
when STATE_START => |
busy_n <= '0'; |
op_ack <= '0'; |
init_reset <= '1'; |
init_reset <= '1'; |
cap_en <= '0'; |
main_sel <= '0'; |
main_cmd <= CMD_NOP; |
main_bank <= "00"; |
486,15 → 502,19
-- this is where reads and writes return to after being completed |
busy_n <= '1'; |
op_ack <= '0'; |
need_ar_rst <= '0'; |
need_ar_rst <= '0'; |
cap_en <= '1'; |
main_sel <= '1'; |
writer_rst <= '1'; |
reader_rst <= '1'; |
if (need_ar = '1') then |
if (need_ar = '1') then |
busy_n <= '0'; |
cmd_state <= STATE_IDLE_AUTO_REFRESH; |
elsif (op = "01" and en = '1') then |
busy_n <= '0'; |
cmd_state <= STATE_READ_ROW_OPEN; |
elsif (op = "10" and en = '1') then |
busy_n <= '0'; |
cmd_state <= STATE_WRITE_ROW_OPEN; |
else |
cmd_state <= cmd_state; |
526,18 → 546,20
end if; |
|
when STATE_WRITE_ROW_OPEN => |
op_ack <= '1'; |
busy_n <= '0'; |
dqs_dir <= '1'; |
dq_dir <= '1'; |
cap_en <= '0'; |
main_cmd <= CMD_ACTIVE; |
main_bank <= addr(25 downto 24); |
main_addr <= addr(23 downto 11); |
main_bank <= addr_save(25 downto 24); |
main_addr <= addr_save(23 downto 11); |
cmd_state <= STATE_WRITE_WAIT_ROW_OPEN; |
|
when STATE_WRITE_WAIT_ROW_OPEN => |
main_cmd <= CMD_NOP; |
main_bank <= addr(25 downto 24); -- timing kludge |
main_addr <= "001" & addr(10 downto 1); -- last bit determines upper/lower byte in word |
main_bank <= addr_save(25 downto 24); -- timing kludge |
main_addr <= "001" & addr_save(10 downto 1); -- last bit determines upper/lower byte in word |
cmd_state <= STATE_WRITE_ISSUE_CMD; |
|
when STATE_WRITE_ISSUE_CMD => |
544,12 → 566,11
writer_rst <= '0'; |
write_reco_rst <= '1'; |
main_cmd <= CMD_WRITE; |
main_bank <= addr(25 downto 24); |
main_addr <= "001" & addr(10 downto 1); -- last bit determines upper/lower byte in word |
main_bank <= addr_save(25 downto 24); |
main_addr <= "001" & addr_save(10 downto 1); -- last bit determines upper/lower byte in word |
cmd_state <= STATE_WRITE_WAIT_RECOVER; |
|
when STATE_WRITE_WAIT_RECOVER => |
op_ack <= '1'; |
write_reco_rst <= '0'; |
main_cmd <= CMD_NOP; |
main_bank <= "00"; |
561,29 → 582,30
end if; |
|
when STATE_READ_ROW_OPEN => |
op_ack <= '1'; |
busy_n <= '0'; |
dqs_dir <= '0'; |
dq_dir <= '0'; |
cap_en <= '0'; |
main_cmd <= CMD_ACTIVE; |
main_bank <= addr(25 downto 24); |
main_addr <= addr(23 downto 11); |
main_bank <= addr_save(25 downto 24); |
main_addr <= addr_save(23 downto 11); |
cmd_state <= STATE_READ_WAIT_ROW_OPEN; |
|
when STATE_READ_WAIT_ROW_OPEN => |
main_cmd <= CMD_NOP; |
main_bank <= addr(25 downto 24); -- timing kludge |
main_addr <= "001" & addr(10 downto 1); -- last bit determines upper/lower byte |
main_bank <= addr_save(25 downto 24); -- timing kludge |
main_addr <= "001" & addr_save(10 downto 1); -- last bit determines upper/lower byte |
cmd_state <= STATE_READ_ISSUE_CMD; |
|
when STATE_READ_ISSUE_CMD => |
read_wait_rst <= '1'; |
main_cmd <= CMD_READ; |
main_bank <= addr(25 downto 24); |
main_addr <= "001" & addr(10 downto 1); -- last bit determines upper/lower byte |
main_bank <= addr_save(25 downto 24); |
main_addr <= "001" & addr_save(10 downto 1); -- last bit determines upper/lower byte |
cmd_state <= STATE_READ_WAIT_CAPTURE; |
|
when STATE_READ_WAIT_CAPTURE => |
op_ack <= '1'; |
read_wait_rst <= '0'; |
reader_rst <= '0'; |
main_cmd <= CMD_NOP; |