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URL https://opencores.org/ocsvn/sdram_controller/sdram_controller/trunk

Subversion Repositories sdram_controller

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  • This comparison shows the changes necessary to convert path 
    /sdram_controller
    from Rev 5 to Rev 6
    ↔ Reverse comparison
  •

Rev 5 → Rev 6

/trunk/sdram_support.vhd
681,7 → 681,6
port (
ioport : inout std_logic_vector(1 downto 0);
dir : in std_logic;
data_o : out std_logic_vector(1 downto 0);
data_i : in std_logic_vector(1 downto 0)
);
end inout_switch_2;
688,7 → 687,6
 
architecture impl of inout_switch_2 is
begin
data_o <= ioport when dir = '0' else "ZZ";
ioport <= data_i when dir = '1' else "ZZ";
end impl;
 
/trunk/sdram_writer.vhd
45,8 → 45,7
data_o : in std_logic_vector(7 downto 0);
dqs : out std_logic_vector(1 downto 0);
dm : out std_logic_vector(1 downto 0);
dq : out std_logic_vector(15 downto 0);
done : out std_logic
dq : out std_logic_vector(15 downto 0)
);
end sdram_writer;
 
95,9 → 94,6
signal data_out : std_logic_vector(15 downto 0);
signal mask_out : std_logic_vector(1 downto 0);
 
signal writer_dqs_done : std_logic := '0';
signal writer_dm_done : std_logic := '0';
begin
148,7 → 144,6
if (rst = '1') then
dqs_fsm_r <= '0';
dqs_fsm_f <= '0';
writer_dqs_done <= '0';
writer_dqs_state <= STATE_WRITER_DQS_0;
elsif (rising_edge(clk180)) then
case writer_dqs_state is
163,7 → 158,6
when STATE_WRITER_DQS_DONE =>
dqs_fsm_r <= '0';
dqs_fsm_f <= '0';
writer_dqs_done <= '1';
writer_dqs_state <= STATE_WRITER_DQS_DONE;
end case;
end if;
181,7 → 175,6
dq_rising <= x"0000";
dm_falling <= "11";
dq_falling <= x"0000";
writer_dm_done <= '0';
writer_dm_state <= STATE_WRITER_DM_0;
elsif (rising_edge(clk)) then
case writer_dm_state is
202,12 → 195,9
when STATE_WRITER_DM_DONE =>
dm_rising <= "00";
dm_falling <= "00";
writer_dm_done <= '1';
writer_dm_state <= STATE_WRITER_DM_DONE;
end case;
end if;
end process;
done <= writer_dqs_done and writer_dm_done;
end impl;
/trunk/sdram.vhd
131,7 → 131,6
port (
ioport : inout std_logic_vector(1 downto 0);
dir : in std_logic;
data_o : out std_logic_vector(1 downto 0);
data_i : in std_logic_vector(1 downto 0)
);
end component;
147,7 → 146,6
component sdram_reader is
port(
clk000 : in std_logic;
clk270 : in std_logic;
rst : in std_logic;
dq : in std_logic_vector(15 downto 0);
167,8 → 165,7
data_o : in std_logic_vector(7 downto 0);
dqs : out std_logic_vector(1 downto 0);
dm : out std_logic_vector(1 downto 0);
dq : out std_logic_vector(15 downto 0);
done : out std_logic
dq : out std_logic_vector(15 downto 0)
);
end component;
 
239,7 → 236,6
signal bank_oddr2_rising : std_logic_vector(1 downto 0) := "00";
signal addr_oddr2_rising : std_logic_vector(12 downto 0) := "0000000000000";
 
signal dqs_in : std_logic_vector(1 downto 0);
signal dqs_out : std_logic_vector(1 downto 0);
signal dqs_dir : std_logic;
 
248,9 → 244,7
signal dq_dir : std_logic;
 
signal reader_rst : std_logic := '1';
 
signal writer_rst : std_logic := '1';
signal writer_done : std_logic := '0';
 
signal dcm_locked : std_logic;
signal clk_000 : std_logic;
365,7 → 359,6
port map(
ioport => dram_dqs,
dir => dqs_dir,
data_o => dqs_in,
data_i => dqs_out
);
423,7 → 416,6
READER: sdram_reader
port map(
clk000 => clk_000,
clk270 => clk_270,
rst => reader_rst,
dq => dq_in,
442,11 → 434,11
data_o => data_i,
dqs => dqs_out,
dm => dram_dm,
dq => dq_out,
done => writer_done
dq => dq_out
);
-- end component allocs
 
 
debug_reg <= x"00";
dram_cs <= '0';
data_o <= data1_o when addr(0) = '1' else data0_o;
489,9 → 481,9
reader_rst <= '1';
if (need_ar = '1') then
cmd_state <= STATE_IDLE_AUTO_REFRESH;
elsif (op = "01") then
elsif (op = "01" and en = '1') then
cmd_state <= STATE_READ_ROW_OPEN;
elsif (op = "10") then
elsif (op = "10" and en = '1') then
cmd_state <= STATE_WRITE_ROW_OPEN;
else
cmd_state <= cmd_state;
/trunk/scratch.vhd
57,19 → 57,14
signal dram_driver_state : DRAM_DRIVER_STATES := STATE0;
 
signal clk_bufd : std_logic;
signal clk133mhz : std_logic;
signal dcm_locked : std_logic;
signal op : std_logic_vector(1 downto 0);
signal addr : std_logic_vector(25 downto 0);
signal op_ack : std_logic;
signal busy_n : std_logic;
signal data_o : std_logic_vector(7 downto 0);
signal data_i : std_logic_vector(7 downto 0);
signal debug : std_logic_vector(7 downto 0);
signal debug : std_logic_vector(7 downto 0);
signal reg0 : std_logic_vector(7 downto 0) := x"55";
begin
 
BUFG_CLK: BUFG
119,7 → 114,7
when STATE1 =>
addr <= "01000000000000000000000111";
data_i <= "10101010";
data_i <= "11111111";
op <= "10";
if (op_ack = '1') then
dram_driver_state <= STATE2;
/trunk/sdram_reader.vhd
37,7 → 37,6
-- floor. If you want to support both sides of the 2 burst or bigger bursts, you'll need to rework this.
entity sdram_reader is
port(
clk000 : in std_logic;
clk270 : in std_logic;
rst : in std_logic;
dq : in std_logic_vector(15 downto 0);

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