URL
https://opencores.org/ocsvn/sgmii/sgmii/trunk
Subversion Repositories sgmii
Compare Revisions
- This comparison shows the changes necessary to convert path
/sgmii/trunk/src/mAltGX
- from Rev 2 to Rev 12
- ↔ Reverse comparison
Rev 2 → Rev 12
/mAltGX.v
14,7 → 14,7
// ************************************************************ |
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! |
// |
// 11.0 Build 157 04/27/2011 SJ Full Version |
// 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition |
// ************************************************************ |
|
|
33,8 → 33,8
//applicable agreement for further details. |
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//alt_c3gxb CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone IV GX" effective_data_rate="1250.0 Mbps" equalization_setting=1 equalizer_dcgain_setting=0 gxb_powerdown_width=1 loopback_mode="none" number_of_channels=1 number_of_quads=1 operation_mode="duplex" pll_bandwidth_type="auto" pll_control_width=1 pll_divide_by="1" pll_inclk_period=8000 pll_multiply_by="5" pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=0 protocol="gige" receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=0 reconfig_pll_control_width=1 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="false" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_channel_width=8 rx_common_mode="0.82v" rx_datapath_protocol="basic" rx_deskew_pattern="0" rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_second_order_loop="false" rx_enable_self_test_mode="false" rx_force_signal_detect="true" rx_loop_1_digital_filter=8 rx_ppmselect=8 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="10100010010101111100" rx_rate_match_pattern2="10101011011010000011" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_signal_detect_loss_threshold=1 rx_signal_detect_threshold=8 rx_signal_detect_valid_threshold=14 rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="false" rx_use_external_termination="false" rx_word_aligner_num_byte=1 starting_channel_number=0 top_module_name="mAltGX" transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_bitslip_enable="false" tx_channel_width=8 tx_clkout_width=1 tx_common_mode="0.65v" tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_slew_rate="medium" tx_transmit_protocol="basic" tx_use_coreclk="false" tx_use_double_data_mode="false" tx_use_external_termination="false" use_calibration_block="true" vod_ctrl_setting=4 cal_blk_clk gxb_powerdown pll_inclk pll_locked reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_disperr rx_errdetect rx_patterndetect rx_rlv rx_syncstatus tx_clkout tx_ctrlenable tx_datain tx_dataout tx_digitalreset intended_device_family="Cyclone IV GX" |
//VERSION_BEGIN 11.0 cbx_alt_c3gxb 2011:04:27:21:07:19:SJ cbx_altclkbuf 2011:04:27:21:07:19:SJ cbx_altiobuf_bidir 2011:04:27:21:07:19:SJ cbx_altiobuf_in 2011:04:27:21:07:19:SJ cbx_altiobuf_out 2011:04:27:21:07:19:SJ cbx_altpll 2011:04:27:21:07:19:SJ cbx_cycloneii 2011:04:27:21:07:19:SJ cbx_lpm_add_sub 2011:04:27:21:07:19:SJ cbx_lpm_compare 2011:04:27:21:07:19:SJ cbx_lpm_decode 2011:04:27:21:07:19:SJ cbx_lpm_mux 2011:04:27:21:07:19:SJ cbx_mgl 2011:04:27:21:11:03:SJ cbx_stingray 2011:04:27:21:07:19:SJ cbx_stratix 2011:04:27:21:07:19:SJ cbx_stratixii 2011:04:27:21:07:19:SJ cbx_stratixiii 2011:04:27:21:07:19:SJ cbx_stratixv 2011:04:27:21:07:19:SJ cbx_util_mgl 2011:04:27:21:07:19:SJ VERSION_END |
//alt_c3gxb CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone IV GX" effective_data_rate="1250.0 Mbps" equalization_setting=5 equalizer_dcgain_setting=0 gxb_powerdown_width=1 loopback_mode="none" number_of_channels=1 number_of_quads=1 operation_mode="duplex" pll_bandwidth_type="auto" pll_control_width=1 pll_divide_by="1" pll_inclk_period=8000 pll_multiply_by="5" pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=0 protocol="gige" receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=0 reconfig_pll_control_width=1 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="false" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_channel_width=8 rx_common_mode="0.82v" rx_datapath_protocol="basic" rx_deskew_pattern="0" rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_second_order_loop="false" rx_enable_self_test_mode="false" rx_force_signal_detect="true" rx_loop_1_digital_filter=8 rx_ppmselect=8 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="10100010010101111100" rx_rate_match_pattern2="10101011011010000011" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_signal_detect_loss_threshold=1 rx_signal_detect_threshold=8 rx_signal_detect_valid_threshold=14 rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="false" rx_use_external_termination="false" rx_word_aligner_num_byte=1 starting_channel_number=0 top_module_name="mAltGX" transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_bitslip_enable="false" tx_channel_width=8 tx_clkout_width=1 tx_common_mode="0.65v" tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_slew_rate="medium" tx_transmit_protocol="basic" tx_use_coreclk="false" tx_use_double_data_mode="false" tx_use_external_termination="false" use_calibration_block="true" vod_ctrl_setting=4 cal_blk_clk gxb_powerdown pll_inclk pll_locked reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_disperr rx_errdetect rx_patterndetect rx_rlv rx_syncstatus tx_clkout tx_ctrlenable tx_datain tx_dataout tx_digitalreset intended_device_family="Cyclone IV GX" |
//VERSION_BEGIN 11.1SP2 cbx_alt_c3gxb 2012:01:25:21:13:53:SJ cbx_altclkbuf 2012:01:25:21:13:53:SJ cbx_altiobuf_bidir 2012:01:25:21:13:53:SJ cbx_altiobuf_in 2012:01:25:21:13:53:SJ cbx_altiobuf_out 2012:01:25:21:13:53:SJ cbx_altpll 2012:01:25:21:13:53:SJ cbx_cycloneii 2012:01:25:21:13:53:SJ cbx_lpm_add_sub 2012:01:25:21:13:53:SJ cbx_lpm_compare 2012:01:25:21:13:53:SJ cbx_lpm_decode 2012:01:25:21:13:53:SJ cbx_lpm_mux 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ cbx_stingray 2012:01:25:21:13:52:SJ cbx_stratix 2012:01:25:21:13:53:SJ cbx_stratixii 2012:01:25:21:13:53:SJ cbx_stratixiii 2012:01:25:21:13:53:SJ cbx_stratixv 2012:01:25:21:13:53:SJ cbx_util_mgl 2012:01:25:21:13:53:SJ VERSION_END |
// synthesis VERILOG_INPUT_VERSION VERILOG_2001 |
// altera message_off 10463 |
|
658,7 → 658,7
receive_pma0.enable_ltr = "false", |
receive_pma0.enable_second_order_loop = "false", |
receive_pma0.eq_dc_gain = 0, |
receive_pma0.eq_setting = 1, |
receive_pma0.eq_setting = 5, |
receive_pma0.force_signal_detect = "true", |
receive_pma0.logical_channel_address = (starting_channel_number + 0), |
receive_pma0.loop_1_digital_filter = 8, |
1022,7 → 1022,7
// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none" |
// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false" |
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" |
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "1250" |
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "1250.0" |
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0" |
// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "1250.0" |
// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100" |
1045,8 → 1045,8
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic" |
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250" |
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic" |
// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0" |
// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0" |
// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "1" |
// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "1" |
// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "1" |
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "125.0" |
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "62.5 125.0" |
1068,7 → 1068,7
// Retrieval info: CONSTANT: GX_CHANNEL_TYPE STRING "" |
// Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "125.0 MHz" |
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX" |
// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "8" |
// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "6" |
// Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "ANY" |
// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none" |
// Retrieval info: CONSTANT: LPM_TYPE STRING "alt_c3gxb" |
1137,7 → 1137,7
// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false" |
// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true" |
// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "4" |
// Retrieval info: CONSTANT: equalization_setting NUMERIC "1" |
// Retrieval info: CONSTANT: equalization_setting NUMERIC "5" |
// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1" |
// Retrieval info: CONSTANT: iqtxrxclk_allowed STRING "" |
// Retrieval info: CONSTANT: number_of_quads NUMERIC "1" |
1209,7 → 1209,7
// Retrieval info: GEN_FILE: TYPE_NORMAL mAltGX.cmp FALSE |
// Retrieval info: GEN_FILE: TYPE_NORMAL mAltGX.bsf FALSE |
// Retrieval info: GEN_FILE: TYPE_NORMAL mAltGX_inst.v FALSE |
// Retrieval info: GEN_FILE: TYPE_NORMAL mAltGX_bb.v FALSE |
// Retrieval info: GEN_FILE: TYPE_NORMAL mAltGX_bb.v TRUE |
// Retrieval info: LIB_FILE: altera_mf |
// Retrieval info: LIB_FILE: cycloneiv_hssi |
// Retrieval info: CBX_MODULE_PREFIX: ON |
/mAltGXReconfig.qip
1,3 → 1,3
set_global_assignment -name IP_TOOL_NAME "ALTGX_RECONFIG" |
set_global_assignment -name IP_TOOL_VERSION "11.0" |
set_global_assignment -name IP_TOOL_VERSION "11.1" |
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "mAltGXReconfig.v"] |
/mAltGX.qip
1,4 → 1,5
set_global_assignment -name IP_TOOL_NAME "ALTGX" |
set_global_assignment -name IP_TOOL_VERSION "11.0" |
set_global_assignment -name IP_TOOL_VERSION "11.1" |
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "mAltGX.v"] |
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mAltGX_bb.v"] |
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mAltGX.ppf"] |
/mAltGXReconfig.v
14,7 → 14,7
// ************************************************************ |
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! |
// |
// 11.0 Build 157 04/27/2011 SJ Full Version |
// 11.1 Build 259 01/25/2012 SP 2 SJ Web Edition |
// ************************************************************ |
|
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34,7 → 34,7
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//alt_c3gxb_reconfig CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone IV GX" ENABLE_BUF_CAL="TRUE" NUMBER_OF_CHANNELS=1 NUMBER_OF_RECONFIG_PORTS=1 RECONFIG_FROMGXB_WIDTH=5 RECONFIG_TOGXB_WIDTH=4 busy reconfig_clk reconfig_fromgxb reconfig_togxb |
//VERSION_BEGIN 11.0 cbx_alt_c3gxb_reconfig 2011:04:27:21:07:19:SJ cbx_alt_cal 2011:04:27:21:07:19:SJ cbx_alt_dprio 2011:04:27:21:07:19:SJ cbx_altsyncram 2011:04:27:21:07:19:SJ cbx_cycloneii 2011:04:27:21:07:19:SJ cbx_lpm_add_sub 2011:04:27:21:07:19:SJ cbx_lpm_compare 2011:04:27:21:07:19:SJ cbx_lpm_counter 2011:04:27:21:07:19:SJ cbx_lpm_decode 2011:04:27:21:07:19:SJ cbx_lpm_mux 2011:04:27:21:07:19:SJ cbx_lpm_shiftreg 2011:04:27:21:07:19:SJ cbx_mgl 2011:04:27:21:11:03:SJ cbx_stratix 2011:04:27:21:07:19:SJ cbx_stratixii 2011:04:27:21:07:19:SJ cbx_stratixiii 2011:04:27:21:07:19:SJ cbx_stratixv 2011:04:27:21:07:19:SJ cbx_util_mgl 2011:04:27:21:07:19:SJ VERSION_END |
//VERSION_BEGIN 11.1SP2 cbx_alt_c3gxb_reconfig 2012:01:25:21:13:53:SJ cbx_alt_cal 2012:01:25:21:13:53:SJ cbx_alt_dprio 2012:01:25:21:13:53:SJ cbx_altsyncram 2012:01:25:21:13:53:SJ cbx_cycloneii 2012:01:25:21:13:53:SJ cbx_lpm_add_sub 2012:01:25:21:13:53:SJ cbx_lpm_compare 2012:01:25:21:13:53:SJ cbx_lpm_counter 2012:01:25:21:13:53:SJ cbx_lpm_decode 2012:01:25:21:13:53:SJ cbx_lpm_mux 2012:01:25:21:13:53:SJ cbx_lpm_shiftreg 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ cbx_stratix 2012:01:25:21:13:53:SJ cbx_stratixii 2012:01:25:21:13:53:SJ cbx_stratixiii 2012:01:25:21:13:53:SJ cbx_stratixv 2012:01:25:21:13:53:SJ cbx_util_mgl 2012:01:25:21:13:53:SJ VERSION_END |
// synthesis VERILOG_INPUT_VERSION VERILOG_2001 |
// altera message_off 10463 |
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41,7 → 41,7
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//alt_dprio address_width=16 CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone IV GX" quad_address_width=9 address busy datain dataout dpclk dpriodisable dprioin dprioload dprioout quad_address rden reset wren wren_data |
//VERSION_BEGIN 11.0 cbx_alt_dprio 2011:04:27:21:07:19:SJ cbx_cycloneii 2011:04:27:21:07:19:SJ cbx_lpm_add_sub 2011:04:27:21:07:19:SJ cbx_lpm_compare 2011:04:27:21:07:19:SJ cbx_lpm_counter 2011:04:27:21:07:19:SJ cbx_lpm_decode 2011:04:27:21:07:19:SJ cbx_lpm_shiftreg 2011:04:27:21:07:19:SJ cbx_mgl 2011:04:27:21:11:03:SJ cbx_stratix 2011:04:27:21:07:19:SJ cbx_stratixii 2011:04:27:21:07:19:SJ VERSION_END |
//VERSION_BEGIN 11.1SP2 cbx_alt_dprio 2012:01:25:21:13:53:SJ cbx_cycloneii 2012:01:25:21:13:53:SJ cbx_lpm_add_sub 2012:01:25:21:13:53:SJ cbx_lpm_compare 2012:01:25:21:13:53:SJ cbx_lpm_counter 2012:01:25:21:13:53:SJ cbx_lpm_decode 2012:01:25:21:13:53:SJ cbx_lpm_shiftreg 2012:01:25:21:13:53:SJ cbx_mgl 2012:01:25:21:15:41:SJ cbx_stratix 2012:01:25:21:13:53:SJ cbx_stratixii 2012:01:25:21:13:53:SJ VERSION_END |
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//synthesis_resources = lpm_compare 3 lpm_counter 1 lpm_decode 1 lut 1 reg 102 |
//synopsys translate_off |