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/src/mSyncFifo.v
0,0 → 1,65
/*
Developed By Subtleware Corporation Pte Ltd 2011
File :
Description :
Remarks :
Revision :
Date Author Description
02/09/12 Jefflieu
*/
 
 
module mSyncFifo #(parameter pDataWidth=8,pPtrWidth=2)
(
input [pDataWidth-1:00] iv_Din,
input i_Wr,
output o_Full,
output o_Empty,
output [pDataWidth-1:00] ov_Q,
input i_Rd,
input i_Clk,
input i_ARst_L);
 
localparam pMemSize=2**pPtrWidth;
reg [pDataWidth-1:00] rv_Ram [0:pMemSize-1];
reg [pPtrWidth-1:00] rv_RdPtr;
reg [pPtrWidth-1:00] rv_WrPtr;
reg [pPtrWidth:00] rv_Cntr;
wire w_WrValid;
wire w_RdValid;
assign o_Full = (rv_Cntr==pMemSize)?1'b1:1'b0;
assign o_Empty = (rv_Cntr==0)?1'b1:1'b0;
assign w_WrValid = (~o_Full) & i_Wr;
assign w_RdValid = (~o_Empty) & i_Rd;
//DualPortRam
always@(posedge i_Clk or negedge i_ARst_L)
if(i_ARst_L==1'b0) begin
rv_RdPtr<={pPtrWidth{1'b0}};
rv_WrPtr<={pPtrWidth{1'b0}};
rv_Cntr <={(pPtrWidth+1){1'b0}};
end else
begin
if(w_WrValid)
begin
rv_WrPtr <= rv_WrPtr+1;
rv_Ram[rv_WrPtr] <= iv_Din;
end
if(w_RdValid)
rv_RdPtr <= rv_RdPtr+1;
if(w_RdValid & (~w_WrValid))
rv_Cntr <= rv_Cntr-1;
else if(w_WrValid & (~w_RdValid))
rv_Cntr <= rv_Cntr+1;
end
assign ov_Q = rv_Ram[rv_RdPtr];
endmodule
/src/mTransmit.v
0,0 → 1,334
/*
Developed By Subtleware Corporation Pte Ltd 2011
File :
Description :
Remarks :
Revision :
Date Author Description
02/09/12 Jefflieu
*/
 
 
`include "SGMIIDefs.v"
 
module mTransmit(
input [02:00] i3_Xmit,
input [15:00] i16_ConfigReg,
input i_TxEN,
input i_TxER,
input [07:00] i8_TxD,
output reg o_Xmitting,
output reg o_TxEven,
output reg [07:00] o8_TxCodeGroupOut,
output o_TxCodeValid,
output reg o_TxCodeCtrl,
input i_CurrentParity,
input i_Clk,
input i_ARst_L);
 
/*
- Transmit order set Statemachine : OSState
*/
localparam stTX_TEST = 24'h000001; //Initial State
localparam stCONFIG_C1A= 24'h000002; //Configuration phase
localparam stCONFIG_C1B= 24'h000004; //Configuration phase
localparam stCONFIG_C1C= 24'h000008; //Configuration phase
localparam stCONFIG_C1D= 24'h000010; //Configuration phase
localparam stCONFIG_C2A= 24'h000020; //Configuration phase
localparam stCONFIG_C2B= 24'h000040; //Configuration phase
localparam stCONFIG_C2C= 24'h000080; //Configuration phase
localparam stCONFIG_C2D= 24'h000100; //Configuration phase
localparam stTX_IDLE = 24'h000200; //IDLE Phase, Trasmitting Comma Character, this is to wait to sync with the MAC's packet
localparam stXMIT_DATA = 24'h000400; //Data Phase, Trasmitting Comma Character
localparam stIDLE_DATA = 24'h000800; //Trasmitting Data Character of /I/ Ordered Set
localparam stTX_SOP = 24'h001000; //Transmitting SOP
localparam stTX_PKT = 24'h002000; //False state
localparam stTX_DATA = 24'h004000; //Transmitting Data
localparam stTX_EOP = 24'h008000; //End of packet without any extension, tramitting T
localparam stTX_EOP_EXT= 24'h010000; //End of packet with extension
localparam stTX_EXT_1 = 24'h020000; //Extend 1 cycle to align the COMMA to Even Code group
localparam stEPD2_NOEXT= 24'h040000; //Second Cycle of EPD, transmitting /R/
localparam stEPD3 = 24'h080000; //Third Cycle of EPD, transmitting /R/
localparam stCARR_EXT = 24'h100000; //Carrier extension
localparam stALIGN_ERR = 24'h200000; //Repeater's state, we don't use this, go straight to START ERR
localparam stSTART_ERR = 24'h400000; //Repeater's state
localparam stTX_ERR = 24'h800000; //Repeater's state
 
reg [23:00] r24_State;
reg [23:00] w24_NxtState;
wire w_XmitChange;
reg [02:00] r3_LstXmit;
reg r_TxEven;
wire w_TxOSIndicate;
wire w_FifoTxEn;
wire w_FifoTxEr;
wire [07:00] w8_FifoData;
wire w_UpdateXmitChange;
wire w_ResetState;
wire r_ToTxData; //This signal used in txIDLE_DATA state to comeback to TXIDLE or TXDATA
wire w_Disparity;
wire [09:00] w10_FifoDin;
wire [09:00] w10_FifoQ;
wire w_FifoRd,w_FifoEmpty;
reg [07:00] r8_TxData;
assign w_XmitChange = (r3_LstXmit!=i3_Xmit)?1'b1:1'b0;
assign w_TxOSIndicate = (r24_State==stCONFIG_C1A||r24_State==stCONFIG_C1B||r24_State==stCONFIG_C1C||
r24_State==stCONFIG_C2A||r24_State==stCONFIG_C2B||r24_State==stCONFIG_C2C||
r24_State==stTX_IDLE||r24_State==stTX_DATA)?1'b0:1'b1;
//assign w_UpdateXmitChange =
//FIFO
assign w10_FifoDin = {i_TxEN,i_TxER,i8_TxD};
assign w_FifoTxEn = w10_FifoQ[9] & (~w_FifoEmpty);
assign w_FifoTxEr = w10_FifoQ[8] & (~w_FifoEmpty);
assign w8_FifoData = w10_FifoQ[7:0];
mSyncFifo #(.pDataWidth(10),.pPtrWidth(2)) u0SyncFifo (
.iv_Din(w10_FifoDin),
.i_Wr((i_TxEN|i_TxER)),
.i_Rd(w_FifoRd),
.o_Empty(w_FifoEmpty),
.o_Full(),
.ov_Q(w10_FifoQ),
.i_Clk(i_Clk),
.i_ARst_L(i_ARst_L));
//END FIFO
assign w_FifoRd = ((w_FifoTxEn && (r24_State==stXMIT_DATA||r24_State==stTX_IDLE)))?1'b0:1'b1;
always@(posedge i_Clk or negedge i_ARst_L)
if(i_ARst_L==1'b0) begin
r24_State <= stTX_TEST;
r3_LstXmit <= 3'b000;
r_TxEven <= 1'b0;
end
else
begin
if(w_UpdateXmitChange) r3_LstXmit <= i3_Xmit;
r24_State <= w24_NxtState;
r_TxEven <= ~r_TxEven;
o_TxEven <= r_TxEven;
end
assign w_UpdateXmitChange = w_ResetState;
assign w_ResetState = (i_ARst_L==1'b0)||(w_XmitChange && (r_TxEven==1'b0) && w_TxOSIndicate);
assign w_Disparity = i_CurrentParity;
always@(*)
begin
if(w_ResetState)
r24_State <= stTX_TEST;
case(r24_State)
stTX_TEST : if(i3_Xmit==`cXmitCONFIG && r_TxEven==1'b0) w24_NxtState <= stCONFIG_C1A; else
if(i3_Xmit==`cXmitIDLE || (i3_Xmit==`cXmitDATA && (w_FifoTxEn || w_FifoTxEr))) w24_NxtState <= stTX_IDLE; else
if(i3_Xmit==`cXmitDATA && (~w_FifoTxEn) && (~w_FifoTxEr)) w24_NxtState <= stXMIT_DATA;
else w24_NxtState <= stTX_TEST;
stCONFIG_C1A : w24_NxtState <= stCONFIG_C1B;
stCONFIG_C1B : w24_NxtState <= stCONFIG_C1C;
stCONFIG_C1C : w24_NxtState <= stCONFIG_C1D;
stCONFIG_C1D : if(i3_Xmit==`cXmitCONFIG) w24_NxtState <= stCONFIG_C2A; else
if(i3_Xmit==`cXmitIDLE || (i3_Xmit==`cXmitDATA && (w_FifoTxEn || w_FifoTxEr))) w24_NxtState <= stTX_IDLE; else
if(i3_Xmit==`cXmitDATA && (~w_FifoTxEn) && (~w_FifoTxEr)) w24_NxtState <= stXMIT_DATA; else
w24_NxtState <= stTX_ERR;
stCONFIG_C2A : w24_NxtState <= stCONFIG_C2B;
stCONFIG_C2B : w24_NxtState <= stCONFIG_C2C;
stCONFIG_C2C : w24_NxtState <= stCONFIG_C2D;
stCONFIG_C2D : if(i3_Xmit==`cXmitCONFIG) w24_NxtState <= stCONFIG_C1A; else
if(i3_Xmit==`cXmitIDLE || (i3_Xmit==`cXmitDATA && (w_FifoTxEn || w_FifoTxEr))) w24_NxtState <= stTX_IDLE; else
if(i3_Xmit==`cXmitDATA && (~w_FifoTxEn) && (~w_FifoTxEr)) w24_NxtState <= stXMIT_DATA; else
w24_NxtState <= stTX_ERR;
stTX_IDLE : w24_NxtState <= stIDLE_DATA;
stIDLE_DATA : if(r_ToTxData==1'b0) begin //Data phase of TX_IDLE
if(i3_Xmit==`cXmitDATA && (~w_FifoTxEn) && (~w_FifoTxEr)) w24_NxtState <= stXMIT_DATA; else
w24_NxtState <= stTX_IDLE;
end
else
begin
if(w_FifoTxEn & (~w_FifoTxEr)) w24_NxtState <= stTX_SOP; else
if(w_FifoTxEn & w_FifoTxEr) w24_NxtState <= stSTART_ERR; else
w24_NxtState <= stXMIT_DATA;
end
stXMIT_DATA : w24_NxtState <= stIDLE_DATA;
stTX_DATA : if(w_FifoTxEn) w24_NxtState <= stTX_DATA; else
if((~w_FifoTxEn) & (~w_FifoTxEr)) w24_NxtState <= stTX_EOP; else
w24_NxtState <= stTX_EOP_EXT;
stTX_SOP : if(w_FifoTxEn) w24_NxtState <= stTX_DATA; else
if((~w_FifoTxEn) & (~w_FifoTxEr)) w24_NxtState <= stTX_EOP; else
w24_NxtState <= stTX_EOP_EXT;
stTX_EOP : w24_NxtState <= stEPD2_NOEXT;
stEPD2_NOEXT : if(r_TxEven) w24_NxtState <= stEPD3; else
w24_NxtState <= stXMIT_DATA;
stEPD3 : w24_NxtState <= stXMIT_DATA;
stTX_EOP_EXT : if(~w_FifoTxEr) w24_NxtState <= stTX_EXT_1; else w24_NxtState <= stCARR_EXT;
stTX_EXT_1 : w24_NxtState <= stEPD2_NOEXT;
stCARR_EXT : if((~w_FifoTxEn) & (~w_FifoTxEr)) w24_NxtState <= stTX_EXT_1; else
if(w_FifoTxEn & (~w_FifoTxEr)) w24_NxtState <= stTX_SOP; else
if(w_FifoTxEn & w_FifoTxEr) w24_NxtState <= stSTART_ERR; else
w24_NxtState <= stCARR_EXT;
//stALIGN_ERR :
stSTART_ERR : w24_NxtState <= stTX_ERR;
stTX_ERR : if(w_FifoTxEn) w24_NxtState <= stTX_DATA; else
if((~w_FifoTxEn) & (~w_FifoTxEr)) w24_NxtState <= stTX_EOP; else
w24_NxtState <= stTX_EOP_EXT;
endcase
end
assign o_TxCodeValid = 1'b1;
always@(posedge i_Clk or negedge i_ARst_L)
if(i_ARst_L==1'b0) begin
o_Xmitting <= 1'b0;
o_TxCodeCtrl <= 1'b0;
o8_TxCodeGroupOut <= 8'h00;
end else begin
case(w24_NxtState)
stTX_TEST : begin
o_Xmitting <= 1'b0;
end
stCONFIG_C1A : begin
o8_TxCodeGroupOut <= `K28_5;
o_TxCodeCtrl <= 1'b1;
end
stCONFIG_C1B : begin
o8_TxCodeGroupOut <= `D21_5;
o_TxCodeCtrl <= 1'b0;
end
stCONFIG_C1C : o8_TxCodeGroupOut <= i16_ConfigReg[07:00];
stCONFIG_C1D : o8_TxCodeGroupOut <= i16_ConfigReg[15:08];
stCONFIG_C2A : begin
o8_TxCodeGroupOut <= `K28_5;
o_TxCodeCtrl <= 1'b1;
end
stCONFIG_C2B : begin
o8_TxCodeGroupOut <= `D2_2;
o_TxCodeCtrl <= 1'b0;
end
stCONFIG_C2C : o8_TxCodeGroupOut <= i16_ConfigReg[07:00];
stCONFIG_C2D : o8_TxCodeGroupOut <= i16_ConfigReg[15:08];
stTX_IDLE : begin
o8_TxCodeGroupOut <= `K28_5;
o_TxCodeCtrl <= 1'b1;
end
stIDLE_DATA : begin
o8_TxCodeGroupOut <= (w_Disparity==1'b0)?`D5_6:`D16_2;//Disparity = 0 means positive
o_TxCodeCtrl <= 1'b0;
end
stXMIT_DATA : begin
o8_TxCodeGroupOut <= `K28_5;
o_TxCodeCtrl <= 1'b1;
end
stTX_DATA : if(((~w_FifoTxEn) & w_FifoTxEr & w8_FifoData != 8'h0F)||(w_FifoTxEn & w_FifoTxEr))
begin
o8_TxCodeGroupOut <= `K30_7;
o_TxCodeCtrl <= 1'b1;
end else
begin
o8_TxCodeGroupOut <= w8_FifoData;
o_TxCodeCtrl <= 1'b0;
end
stTX_SOP : begin
o_Xmitting <= 1'b1;
o8_TxCodeGroupOut <= `K27_7;
o_TxCodeCtrl <= 1'b1;
end
stTX_EOP : begin
o8_TxCodeGroupOut <= `K29_7;
o_TxCodeCtrl <= 1'b1;
o_Xmitting <= (~r_TxEven);
end
stEPD2_NOEXT : begin
o8_TxCodeGroupOut <= `K23_7;
o_TxCodeCtrl <= 1'b1;
o_Xmitting <= 1'b0;
end
stEPD3 : begin
o8_TxCodeGroupOut <= `K23_7;
o_TxCodeCtrl <= 1'b1;
end
stTX_EOP_EXT : if(((~w_FifoTxEn) & w_FifoTxEr & w8_FifoData != 8'h0F)||(w_FifoTxEn & w_FifoTxEr))
begin
o8_TxCodeGroupOut <= `K30_7;
o_TxCodeCtrl <= 1'b1;
end else
begin
o8_TxCodeGroupOut <= `K29_7;
o_TxCodeCtrl <= 1'b1;
end
stTX_EXT_1 : begin
o_Xmitting <= (~r_TxEven);
if(((~w_FifoTxEn) & w_FifoTxEr & w8_FifoData != 8'h0F)||(w_FifoTxEn & w_FifoTxEr))
begin
o8_TxCodeGroupOut <= `K30_7;
o_TxCodeCtrl <= 1'b1;
end else
begin
o8_TxCodeGroupOut <= `K23_7;
o_TxCodeCtrl <= 1'b1;
end
end
stCARR_EXT : if(((~w_FifoTxEn) & w_FifoTxEr & w8_FifoData != 8'h0F)||(w_FifoTxEn & w_FifoTxEr))
begin
o8_TxCodeGroupOut <= `K30_7;
o_TxCodeCtrl <= 1'b1;
end else
begin
o8_TxCodeGroupOut <= `K23_7;
o_TxCodeCtrl <= 1'b1;
end
//stALIGN_ERR :
stSTART_ERR : begin
o8_TxCodeGroupOut <= `K27_7;
o_TxCodeCtrl <= 1'b1;
o_Xmitting <= 1'b1;
end
stTX_ERR : begin
o8_TxCodeGroupOut <= `K30_7;
o_TxCodeCtrl <= 1'b1;
end
endcase
end
//synthesis translate_off
reg [239:0] r240_TxStateName;
always@(*)
case(r24_State)
stTX_TEST : r240_TxStateName<="stTX_TEST ";
stCONFIG_C1A : r240_TxStateName<="stCONFIG_C1A";
stCONFIG_C1B : r240_TxStateName<="stCONFIG_C1B";
stCONFIG_C1C : r240_TxStateName<="stCONFIG_C1C";
stCONFIG_C1D : r240_TxStateName<="stCONFIG_C1D";
stCONFIG_C2A : r240_TxStateName<="stCONFIG_C2A";
stCONFIG_C2B : r240_TxStateName<="stCONFIG_C2B";
stCONFIG_C2C : r240_TxStateName<="stCONFIG_C2C";
stCONFIG_C2D : r240_TxStateName<="stCONFIG_C2D";
stTX_IDLE : r240_TxStateName<="stTX_IDLE ";
stXMIT_DATA : r240_TxStateName<="stXMIT_DATA";
stIDLE_DATA : r240_TxStateName<="stIDLE_DATA";
stTX_SOP : r240_TxStateName<="stTX_SOP ";
stTX_PKT : r240_TxStateName<="stTX_PKT ";
stTX_DATA : r240_TxStateName<="stTX_DATA ";
stTX_EOP : r240_TxStateName<="stTX_EOP ";
stTX_EOP_EXT : r240_TxStateName<="stTX_EOP_EXT";
stTX_EXT_1 : r240_TxStateName<="stTX_EXT_1 ";
stEPD2_NOEXT : r240_TxStateName<="stEPD2_NOEXT";
stEPD3 : r240_TxStateName<="stEPD3 ";
stCARR_EXT : r240_TxStateName<="stCARR_EXT ";
stALIGN_ERR : r240_TxStateName<="stALIGN_ERR";
stSTART_ERR : r240_TxStateName<="stSTART_ERR";
stTX_ERR : r240_TxStateName<="stTX_ERR ";
endcase
//synthesis translate_on
endmodule
/src/mSyncCtrl.v
0,0 → 1,191
/*
Developed By Subtleware Corporation Pte Ltd 2011
File :
Description :
Remarks :
Revision :
Date Author Description
02/09/12 Jefflieu
*/
 
`include "SGMIIDefs.v"
module mSyncCtrl (
input i_Clk,
input i_Cke,
input i_ARst_L,
input i_CtrlLoopBack,
 
input [07:00] i8_RxCodeGroupIn,
input i_RxCodeInvalid,
input i_RxCodeCtrl,
input i_SignalDetect,
output reg [07:00] o8_RxCodeGroupOut,
output o_RxEven,
output reg o_RxCodeInvalid,
output reg o_RxCodeCtrl,
output reg o_SyncStatus,
output o_BitSlip,
output o_IsComma,
output o_OrderedSetValid,
output o_IsI1Set,
output o_IsI2Set,
output o_IsC1Set,
output o_IsC2Set,
output reg o_IsTSet,
output reg o_IsVSet,
output reg o_IsSSet,
output reg o_IsRSet);
 
localparam stLOSS_OF_SYNC = 13'h0001;
localparam stCOMMA_DTEC_1 = 13'h0002;
localparam stACQ_SYNC_1 = 13'h0004;
localparam stCOMMA_DTEC_2 = 13'h0008;
localparam stACQ_SYNC_2 = 13'h0010;
localparam stCOMMA_DTEC_3 = 13'h0020;
localparam stSYNC_ACQUIRED_1 = 13'h0040;
localparam stSYNC_ACQUIRED_2 = 13'h0080;
localparam stSYNC_ACQUIRED_2A = 13'h0100;
localparam stSYNC_ACQUIRED_3 = 13'h0100;
localparam stSYNC_ACQUIRED_3A = 13'h0400;
localparam stSYNC_ACQUIRED_4 = 13'h0800;
localparam stSYNC_ACQUIRED_4A = 13'h1000;
 
reg [12:00] r13_State;
reg r_RxEven;
wire w_SignalDetectChange;
reg r_LastSignalDetect;
reg [02:00] r3_GoodCgs;
wire w_CgBad;
wire w_IsComma;
wire w_IsData;
reg r_IsComma;
wire w_IsC1Set;
wire w_IsC2Set;
wire w_IsI1Set;
wire w_IsI2Set;
wire w_IsRSet;
wire w_IsSSet;
wire w_IsTSet;
wire w_IsVSet;
reg r_IsRSTV;
wire [3:0] w4_ID1;
reg [3:0] r4_ID2;
 
//MainStatemachine
assign w_IsComma = (~i_RxCodeInvalid) && (i_RxCodeCtrl) && (i8_RxCodeGroupIn==8'hBC||i8_RxCodeGroupIn==8'h3C||i8_RxCodeGroupIn==8'hFC);
assign w_IsData = (~i_RxCodeInvalid) && (~i_RxCodeCtrl);
assign w_CgBad = i_RxCodeInvalid|(w_IsComma & r_RxEven);
assign w_SignalDetectChange = r_LastSignalDetect^i_SignalDetect;
always@(posedge i_Clk or negedge i_ARst_L)
begin: MainStatemachine
if(i_ARst_L==1'b0) begin
r13_State <= stLOSS_OF_SYNC;
end
else if(i_Cke) begin
r_LastSignalDetect <= i_SignalDetect;
if(w_SignalDetectChange & (~i_RxCodeInvalid) & ~i_CtrlLoopBack)
r13_State <= stLOSS_OF_SYNC;
else
case(r13_State)
stLOSS_OF_SYNC : if(w_IsComma && (i_SignalDetect||i_CtrlLoopBack)) r13_State <= stCOMMA_DTEC_1;
stCOMMA_DTEC_1 : if(w_IsData) r13_State <= stACQ_SYNC_1; else r13_State <= stLOSS_OF_SYNC;
stACQ_SYNC_1 : if(w_CgBad) r13_State <= stLOSS_OF_SYNC; else
if(r_RxEven==1'b0 && w_IsComma) r13_State <= stCOMMA_DTEC_2;
stCOMMA_DTEC_2 : if(w_IsData) r13_State <= stACQ_SYNC_2; else r13_State <= stLOSS_OF_SYNC;
stACQ_SYNC_2 : if(w_CgBad) r13_State <= stLOSS_OF_SYNC; else
if(r_RxEven==1'b0 && w_IsComma) r13_State <= stCOMMA_DTEC_3;
stCOMMA_DTEC_3 : if(w_IsData) r13_State <= stSYNC_ACQUIRED_1; else r13_State <= stLOSS_OF_SYNC;
stSYNC_ACQUIRED_1 : if(w_CgBad) r13_State <= stSYNC_ACQUIRED_2;
stSYNC_ACQUIRED_2 : if(w_CgBad) r13_State <= stSYNC_ACQUIRED_3; else r13_State <= stSYNC_ACQUIRED_2A;
stSYNC_ACQUIRED_2A : if(w_CgBad) r13_State <= stSYNC_ACQUIRED_3; else
if(r3_GoodCgs==3) r13_State <= stSYNC_ACQUIRED_1;
stSYNC_ACQUIRED_3 : if(w_CgBad) r13_State <= stSYNC_ACQUIRED_4; else r13_State <= stSYNC_ACQUIRED_3A;
stSYNC_ACQUIRED_3A : if(w_CgBad) r13_State <= stSYNC_ACQUIRED_4; else
if(r3_GoodCgs==3) r13_State <= stSYNC_ACQUIRED_2;
stSYNC_ACQUIRED_4 : if(w_CgBad) r13_State <= stLOSS_OF_SYNC; else r13_State <= stSYNC_ACQUIRED_4A;
stSYNC_ACQUIRED_4A : if(w_CgBad) r13_State <= stLOSS_OF_SYNC; else
if(r3_GoodCgs==3) r13_State <= stSYNC_ACQUIRED_3;
endcase
end
end
 
always@(posedge i_Clk or negedge i_ARst_L)
begin: SignalControl
if(i_ARst_L==1'b0) begin
r_RxEven <= 1'b0;
end
else if(i_Cke) begin
if((r13_State==stLOSS_OF_SYNC&&(w_IsComma && (i_SignalDetect||i_CtrlLoopBack)))||
((r13_State==stACQ_SYNC_1||r13_State==stACQ_SYNC_2)&&(r_RxEven==1'b0 && w_IsComma)))
r_RxEven<=1'b1;
else
r_RxEven <= ~r_RxEven;
if(r13_State==stSYNC_ACQUIRED_1)
o_SyncStatus <= 1'b1;
else if(r13_State==stLOSS_OF_SYNC)
o_SyncStatus <= 1'b0;
if(r13_State==stSYNC_ACQUIRED_2A||r13_State==stSYNC_ACQUIRED_3A||r13_State==stSYNC_ACQUIRED_4A)
r3_GoodCgs <= r3_GoodCgs+3'h1;
else if(r13_State==stSYNC_ACQUIRED_2||r13_State==stSYNC_ACQUIRED_3||r13_State==stSYNC_ACQUIRED_4)
r3_GoodCgs <= 3'h0;
o8_RxCodeGroupOut <= i8_RxCodeGroupIn;
o_RxCodeInvalid <= i_RxCodeInvalid;
o_RxCodeCtrl <= i_RxCodeCtrl;
end
end
assign o_RxEven = r_RxEven;
 
//ordered set detection
assign o_OrderedSetValid = r_IsComma | r_IsRSTV;
assign w_IsC1Set = r_IsComma && w_IsData && (i8_RxCodeGroupIn==`D21_5);
assign w_IsC2Set = r_IsComma && w_IsData && (i8_RxCodeGroupIn==`D2_2);
assign w_IsI1Set = r_IsComma && w_IsData && (i8_RxCodeGroupIn==`D5_6);
assign w_IsI2Set = r_IsComma && w_IsData && (i8_RxCodeGroupIn==`D16_2);
assign w_IsRSet = i_RxCodeCtrl && (~i_RxCodeInvalid) && (i8_RxCodeGroupIn==`K23_7);
assign w_IsSSet = i_RxCodeCtrl && (~i_RxCodeInvalid) && (i8_RxCodeGroupIn==`K27_7);
assign w_IsTSet = i_RxCodeCtrl && (~i_RxCodeInvalid) && (i8_RxCodeGroupIn==`K29_7);
assign w_IsVSet = i_RxCodeCtrl && (~i_RxCodeInvalid) && (i8_RxCodeGroupIn==`K30_7);
assign o_IsC1Set = w_IsC1Set;
assign o_IsC2Set = w_IsC2Set;
assign o_IsI1Set = w_IsI1Set;
assign o_IsI2Set = w_IsI2Set;
assign o_IsComma = r_IsComma;
always@(posedge i_Clk or negedge i_ARst_L )
if(!i_ARst_L) begin
r_IsComma <= 1'b0;
r_IsRSTV <= 1'b0;
end else begin
r_IsComma <= w_IsComma;
r_IsRSTV <= w_IsRSet | w_IsSSet | w_IsTSet | w_IsVSet;
o_IsRSet <= w_IsRSet;
o_IsSSet <= w_IsSSet;
o_IsTSet <= w_IsTSet;
o_IsVSet <= w_IsVSet;
end
//synthesis translate_off
reg [239:0] r240_SyncStateName;
always@(*)
case(r13_State)
stLOSS_OF_SYNC : r240_SyncStateName<="stLOSS_OF_SYNC ";
stCOMMA_DTEC_1 : r240_SyncStateName<="stCOMMA_DTEC_1 ";
stACQ_SYNC_1 : r240_SyncStateName<="stACQ_SYNC_1 ";
stCOMMA_DTEC_2 : r240_SyncStateName<="stCOMMA_DTEC_2 ";
stACQ_SYNC_2 : r240_SyncStateName<="stACQ_SYNC_2 ";
stCOMMA_DTEC_3 : r240_SyncStateName<="stCOMMA_DTEC_3 ";
stSYNC_ACQUIRED_1 : r240_SyncStateName<="stSYNC_ACQUIRED_1 ";
stSYNC_ACQUIRED_2 : r240_SyncStateName<="stSYNC_ACQUIRED_2 ";
stSYNC_ACQUIRED_2A : r240_SyncStateName<="stSYNC_ACQUIRED_2A ";
stSYNC_ACQUIRED_3 : r240_SyncStateName<="stSYNC_ACQUIRED_3 ";
stSYNC_ACQUIRED_3A : r240_SyncStateName<="stSYNC_ACQUIRED_3A ";
stSYNC_ACQUIRED_4 : r240_SyncStateName<="stSYNC_ACQUIRED_4 ";
stSYNC_ACQUIRED_4A : r240_SyncStateName<="stSYNC_ACQUIRED_4A ";
endcase
//synthesis translate_on
endmodule
/src/mReceive.v
0,0 → 1,326
/*
Developed By Subtleware Corporation Pte Ltd 2011
File :
Description :
Remarks :
Revision :
Date Author Description
02/09/12 Jefflieu
*/
`include "SGMIIDefs.v"
 
module mReceive(
 
input [07:00] i8_RxCodeGroupIn,
input i_RxCodeInvalid,
input i_RxCodeCtrl,
input i_RxEven,
input i_IsComma,
input [02:00] i3_Xmit,
input i_OrderedSetValid,
input i_IsI1Set,
input i_IsI2Set,
input i_IsC1Set,
input i_IsC2Set,
input i_IsTSet,
input i_IsVSet,
input i_IsSSet,
input i_IsRSet,
input i_CheckEndKDK,
input i_CheckEndKD21_5D0_0,
input i_CheckEndKD2_2D0_0,
input i_CheckEndTRK,
input i_CheckEndTRR,
input i_CheckEndRRR,
input i_CheckEndRRK,
input i_CheckEndRRS,
output reg [15:00] o16_RxConfigReg,
output o_RUDIConfig,
output o_RUDIIdle,
output o_RUDIInvalid,
output reg o_RxDV,
output reg o_RxER,
output reg [07:00] o8_RxD,
output reg o_Invalid,
output reg o_Receiving,
input i_Clk,
input i_ARst_L
);
 
localparam stWAIT_FOR_K = 21'h000001,
stRX_K = 21'h000002,
stRX_CB = 21'h000004,
stRX_CC = 21'h000008,
stRX_CD = 21'h000010,
stRX_INVALID = 21'h000020,
stIDLE_D = 21'h000040,
stCARRIER_DTEC = 21'h000080,
stFALSE_CARRIER = 21'h000100,
stSTART_OF_PKT = 21'h000200,
stRECEIVE = 21'h000400,
stEARLY_END = 21'h000800,
stTRI_RRI = 21'h001000,
stTRR_EXTEND = 21'h002000,
stEPD2_CHK_END = 21'h004000,
stPKT_BURST_RRS = 21'h008000,
stRX_DATA_ERR = 21'h010000,
stRX_DATA = 21'h020000,
stEARLY_END_EXT = 21'h040000,
stEXT_ERROR = 21'h080000,
stLINK_FAILED = 21'h100000;
reg [20:00] r21_State;
reg [20:00] r21_NxtState;
 
wire wSUDIK28_5;
wire wSUDID21_5;
wire wSUDID2_2;
wire wCarrierDtect;//what is this
wire wSUDI;
 
wire w_IsC1Set;
wire w_IsC2Set;
wire w_IsI1Set;
wire w_IsI2Set;
wire w_IsRSet;
wire w_IsSSet;
wire w_IsTSet;
wire w_IsVSet;
 
//synthesis translate_off
reg [8*30-1:0] rvStateName;
always@(*)
begin
case(r21_State)
stWAIT_FOR_K : rvStateName <= "Wait For K";
stRX_K : rvStateName <= "RX K";
stRX_CB : rvStateName <= "RX CB";
stRX_CC : rvStateName <= "RX CC";
stRX_CD : rvStateName <= "RX CD";
stRX_INVALID : rvStateName <= "RX Invalid";
stIDLE_D : rvStateName <= "IDLE D";
stCARRIER_DTEC : rvStateName <= "CARRIER DETECT";
stFALSE_CARRIER : rvStateName <= "FALSE CARRIER";
stSTART_OF_PKT : rvStateName <= "Start of Packet";
stRECEIVE : rvStateName <= "Receiving";
stEARLY_END : rvStateName <= "Early End";
stTRI_RRI : rvStateName <= "TRI RRI";
stTRR_EXTEND : rvStateName <= "TRR Extend";
stEPD2_CHK_END : rvStateName <= "EPD2 Check End";
stPKT_BURST_RRS : rvStateName <= "PKT BURST RRS";
stRX_DATA_ERR : rvStateName <= "RX DATA Error";
stRX_DATA : rvStateName <= "RX DATA";
stEARLY_END_EXT : rvStateName <= "Early End Ext";
stEXT_ERROR : rvStateName <= "Ext Error";
stLINK_FAILED : rvStateName <= "Link Failed";
endcase
//$display("mReceive State: %s",rvStateName);
end
//synthesis translate_on
 
assign w_IsSSet = i_OrderedSetValid && i_IsRSet;
assign wSUDI = ~i_RxCodeInvalid;
assign wCarrierDtect = i_IsRSet|i_IsSSet|i_IsTSet|i_IsVSet;
always@(posedge i_Clk or negedge i_ARst_L)
if(i_ARst_L==1'b0) begin
r21_State <= stWAIT_FOR_K;
end else begin
r21_State <= r21_NxtState;
end
assign wSUDIK28_5 = (!i_RxCodeInvalid) && (i_RxCodeCtrl) && (i8_RxCodeGroupIn==`K28_5);
assign wSUDID21_5 = (!i_RxCodeInvalid) && (!i_RxCodeCtrl) && (i8_RxCodeGroupIn==`D21_5);
assign wSUDID2_2 = (!i_RxCodeInvalid) && (!i_RxCodeCtrl) && (i8_RxCodeGroupIn==`D2_2);
always@(*)
begin
case(r21_State)
stWAIT_FOR_K: if(i_IsComma && i_RxEven) r21_NxtState <= stRX_K; else r21_NxtState<=stWAIT_FOR_K;
stRX_K : if(wSUDID21_5||wSUDID2_2)
r21_NxtState <= stRX_CB; else
if((!i_RxCodeInvalid) && i_RxCodeCtrl && i3_Xmit!=`cXmitDATA)
r21_NxtState <= stRX_INVALID; else
if(((!i_RxCodeInvalid) && (!i_RxCodeCtrl) && i3_Xmit!=`cXmitDATA && i8_RxCodeGroupIn!=`D21_5 && i8_RxCodeGroupIn!=`D2_2)||
((!i_RxCodeInvalid) && i3_Xmit==`cXmitDATA && ((i8_RxCodeGroupIn!=`D21_5 && i8_RxCodeGroupIn!=`D2_2 && (!i_RxCodeCtrl))||i_RxCodeCtrl)))
r21_NxtState <= stIDLE_D; else
r21_NxtState <= stRX_K;
stRX_CB : if((!i_RxCodeInvalid) && (!i_RxCodeCtrl)) r21_NxtState <= stRX_CC; else r21_NxtState <= stRX_INVALID;
stRX_CC : if((!i_RxCodeInvalid) && (!i_RxCodeCtrl)) r21_NxtState <= stRX_CD; else r21_NxtState <= stRX_INVALID;
stRX_CD : if((!i_RxCodeInvalid) && (i_RxCodeCtrl) && i8_RxCodeGroupIn==`K28_5 && i_RxEven)
r21_NxtState <= stRX_K;
else
r21_NxtState <= stRX_INVALID;
stRX_INVALID: if(wSUDIK28_5 && i_RxEven)
r21_NxtState <= stRX_K;
else
r21_NxtState <= stWAIT_FOR_K;
stIDLE_D : if(!wSUDIK28_5 && (i3_Xmit!=`cXmitDATA))
r21_NxtState <= stRX_INVALID;
else if(!i_RxCodeInvalid && i3_Xmit==`cXmitDATA && i_IsSSet)
r21_NxtState <= stSTART_OF_PKT;
else if((!i_RxCodeInvalid && i3_Xmit==`cXmitDATA && (~wCarrierDtect)) || (wSUDIK28_5 && i_RxEven))
r21_NxtState <= stRX_K;
else
r21_NxtState <= stFALSE_CARRIER;
/*stCARRIER_DTEC: if(i_OrderedSetValid && i_IsSSet)
r21_NxtState <= stSTART_OF_PKT;
else
r21_NxtState <= stFALSE_CARRIER;*/
stFALSE_CARRIER : if(wSUDIK28_5 && i_RxEven) r21_NxtState <= stRX_K; else r21_NxtState <= stFALSE_CARRIER;
stSTART_OF_PKT : if(wSUDI)
begin
if(~i_RxCodeCtrl) r21_NxtState <= stRX_DATA; else
if((i_CheckEndKDK||i_CheckEndKD21_5D0_0||i_CheckEndKD2_2D0_0) &&i_RxEven)
r21_NxtState <= stEARLY_END; else
if(i_CheckEndTRK && i_RxEven) r21_NxtState <= stTRI_RRI; else
if(i_CheckEndTRR) r21_NxtState <= stTRR_EXTEND; else
if(i_CheckEndRRR) r21_NxtState <= stEARLY_END_EXT; else
r21_NxtState <= stRX_DATA_ERR;
end
else r21_NxtState <= stRX_DATA_ERR;
//stRECEIVE : //zero cycle state
stRX_DATA : if(wSUDI)
begin
if(~i_RxCodeCtrl) r21_NxtState <= stRX_DATA; else
if((i_CheckEndKDK||i_CheckEndKD21_5D0_0||i_CheckEndKD2_2D0_0) &&i_RxEven)
r21_NxtState <= stEARLY_END; else
if(i_CheckEndTRK && i_RxEven) r21_NxtState <= stTRI_RRI; else
if(i_CheckEndTRR) r21_NxtState <= stTRR_EXTEND; else
if(i_CheckEndRRR) r21_NxtState <= stEARLY_END_EXT; else
r21_NxtState <= stRX_DATA_ERR;
end
else r21_NxtState <= stRX_DATA_ERR;
stRX_DATA_ERR : if(wSUDI)
begin
if(~i_RxCodeCtrl) r21_NxtState <= stRX_DATA; else
if((i_CheckEndKDK||i_CheckEndKD21_5D0_0||i_CheckEndKD2_2D0_0) &&i_RxEven)
r21_NxtState <= stEARLY_END; else
if(i_CheckEndTRK && i_RxEven) r21_NxtState <= stTRI_RRI; else
if(i_CheckEndTRR) r21_NxtState <= stTRR_EXTEND; else
if(i_CheckEndRRR) r21_NxtState <= stEARLY_END_EXT; else
r21_NxtState <= stRX_DATA_ERR;
end
else r21_NxtState <= stRX_DATA_ERR;
stEARLY_END : if(wSUDID21_5||wSUDID2_2) r21_NxtState <= stRX_CB; else r21_NxtState <= stIDLE_D;
stTRI_RRI : if(wSUDIK28_5) r21_NxtState <= stRX_K; else r21_NxtState <= stTRI_RRI;
stTRR_EXTEND : if(i_CheckEndRRR) r21_NxtState <= stTRR_EXTEND; else
if(i_CheckEndRRK && i_RxEven) r21_NxtState <= stTRI_RRI; else
if(i_CheckEndRRS) r21_NxtState <= stPKT_BURST_RRS; else
if(i_IsVSet) r21_NxtState <= stEXT_ERROR; else
r21_NxtState <= stTRR_EXTEND;
stEARLY_END_EXT : if(i_CheckEndRRR) r21_NxtState <= stTRR_EXTEND; else
if(i_CheckEndRRK && i_RxEven) r21_NxtState <= stTRI_RRI; else
if(i_CheckEndRRS) r21_NxtState <= stPKT_BURST_RRS; else
if(i_IsVSet) r21_NxtState <= stEXT_ERROR; else
r21_NxtState <= stEARLY_END_EXT;
//This is zero cycle state
//stEPD2_CHK_END : if(i_CheckEndRRR) r21_NxtState <= stTRR_EXTEND; else
// if(i_CheckEndRRK && i_RxEven) r21_NxtState <= stTRI_RRI; else
// if(i_CheckEndRRS) r21_NxtState <= stPKT_BURST_RRS; else
// r21_NxtState <= stEXT_ERROR;
stPKT_BURST_RRS : if(i_IsSSet && i_OrderedSetValid && wSUDI) r21_NxtState <= stSTART_OF_PKT; else r21_NxtState <= stPKT_BURST_RRS;
stEXT_ERROR : if(i_IsSSet && i_OrderedSetValid && wSUDI) r21_NxtState <= stSTART_OF_PKT; else
if(wSUDIK28_5 && i_RxEven) r21_NxtState <= stRX_K; else
if(i_CheckEndRRR) r21_NxtState <= stTRR_EXTEND; else
if(i_CheckEndRRK && i_RxEven) r21_NxtState <= stTRI_RRI; else
if(i_CheckEndRRS) r21_NxtState <= stPKT_BURST_RRS; else
r21_NxtState <= stEXT_ERROR;
endcase
end
 
assign o_RUDIConfig = (r21_State==stRX_CD )?1'b1:1'b0;
assign o_RUDIIdle = (r21_State==stIDLE_D )?1'b1:1'b0;
assign o_RUDIInvalid= (r21_State==stRX_INVALID && i3_Xmit==`cXmitCONFIG)?1'b1:1'b0;
 
always@(posedge i_Clk or negedge i_ARst_L)
if(i_ARst_L==1'b0) begin
o_Receiving <= 1'b0;
o_RxDV <= 1'b0;
o_RxER <= 1'b0;
o8_RxD <= 8'h0;
o16_RxConfigReg <= 16'h00;
end else begin
case(r21_NxtState)
//stWAIT_FOR_K :
stRX_K : begin
o_Receiving <= 1'b0;
o_RxDV <= 1'b0;
o_RxER <= 1'b0;
end
//stRX_CB :
stRX_CC : o16_RxConfigReg[07:00] <= i8_RxCodeGroupIn;
stRX_CD : o16_RxConfigReg[15:08] <= i8_RxCodeGroupIn;
stRX_INVALID : if(i3_Xmit==`cXmitDATA) o_Receiving <= 1'b1;
stIDLE_D : begin
o_Receiving <= 1'b0;
o_RxDV <= 1'b0;
o_RxER <= 1'b0;
end
//stCARRIER_DTEC: o_Receiving <= 1'b1;
stFALSE_CARRIER : begin
o_RxER <= 1'b1;
o8_RxD <= 8'h0E;
end
stSTART_OF_PKT : begin
o_Receiving <= 1'b1;
o_RxDV <= 1'b1;
o_RxER <= 1'b0;
o8_RxD <= 8'h55;
end
//stRECEIVE :
stEARLY_END : o_RxER <= 1'b1;
stTRI_RRI : begin
o_Receiving <= 1'b0;
o_RxER <= 1'b0;
o_RxDV <= 1'b0;
end
stTRR_EXTEND : begin
o_RxER <= 1'b1;
o_RxDV <= 1'b0;
o8_RxD <= 8'h0F;
end
//stEPD2_CHK_END :
stPKT_BURST_RRS : begin
o_RxDV <= 1'b0;
o8_RxD <= 8'b0000_1111;
end
stRX_DATA_ERR : o_RxER <= 1'b1;
stRX_DATA : begin
o_RxER <= 1'b0;
o8_RxD <= i8_RxCodeGroupIn;
end
stEARLY_END_EXT : o_RxER <= 1'b1;
stEXT_ERROR : begin
o_RxDV <= 1'b0;
o8_RxD <= 8'b0001_1111;
end
stLINK_FAILED : begin
if(o_Receiving==1'b1)
begin
o_Receiving <= 1'b0;
o_RxER <= 1'b1;
end else
begin
o_RxDV <= 1'b0;
o_RxER <= 1'b0;
end
if(i3_Xmit!=`cXmitDATA) o_Invalid <= 1'b1;
end
endcase
end
endmodule
/src/mANCtrl.v
0,0 → 1,220
/*
Developed By Subtleware Corporation Pte Ltd 2011
File :
Description :
Remarks : No Support for Next Page
Revision :
Date Author Description
02/09/12 Jefflieu
*/
 
`include "SGMIIDefs.v"
 
`timescale 1ns/100ps
 
 
`define c10ms (10_000_000/`cSystemClkPeriod)
`define c1p6ms (00_001_000/`cSystemClkPeriod)
 
 
 
 
module mANCtrl(
input i_Clk,
input i_ARst_L,
input i_Cke,
input i_RestartAN,
input i_SyncStatus,
input i_ANEnable,
input [20:00] i21_LinkTimer,
output [15:00] o16_LpAdvAbility,
input [16:01] i16_LcAdvAbility,
input [15:00] i16_RxConfigReg,
input i_RUDIConfig,
input i_RUDIIdle,
input i_RUDIInvalid,
output o_ANComplete,
output reg [02:00] o3_Xmit,
output reg [15:00] o16_TxConfigReg);
localparam stAN_ENABLE = 8'h01,
stAN_RESTART = 8'h02,
stABILITY_DTECT = 8'h04,
stACK_DTECT = 8'h08,
stCMPLT_ACK = 8'h10,
stIDLE_DTECT = 8'h20,
stLINK_OK = 8'h40,
stAN_DIS_LINKOK = 8'h80;
 
reg [20:00] r21_LinkTimer;
reg [02:00] r2_RxCfgRegMchCntr;
wire w_AbiMatch;
reg r_ConsistencyMatch;
wire w_AckMatch;
reg [07:00] r8_State;
reg r_ANEable;
wire w_LinkTimerDone;
reg [16:01] r16_LpAdvAbility; //Link partner Advertised Ability, updated every time RUDIConfig is valid
reg r_NxtPage;
reg r_NxtPageLoaded;
reg r_ToggleTx;
reg r_ToggleRx;
reg [01:00] r2_AbilityMatchCnt;
reg [01:00] r2_ConsistMatchCnt;
reg [01:00] r2_AcknowlMatchCnt;
reg [15:00] r16_AbilityReg; //Captured of Partner Ability before going to Acknowledge Detect
reg [01:00] r2_IdleMatchCnt;
wire w_IdleMatch;
assign w_LinkTimerDone = (r21_LinkTimer==i21_LinkTimer)?1'b1:1'b0;
assign w_AbiMatch = (r2_AbilityMatchCnt==2'b11)?1'b1:1'b0;
assign w_AckMatch = (r2_AcknowlMatchCnt==2'b11)?1'b1:1'b0;
assign w_IdleMatch = (r2_IdleMatchCnt==2'b11)?1'b1:1'b0;
assign o16_LpAdvAbility = r16_LpAdvAbility;
assign o_ANComplete = (r8_State==stLINK_OK)?1'b1:1'b0;
always@(posedge i_Clk or negedge i_ARst_L)
if(i_ARst_L==1'b0) begin
r8_State <= stAN_ENABLE;
end else begin
r_ANEable <= i_ANEnable;
if((~i_Cke) || i_RestartAN || (~i_SyncStatus) || i_RUDIInvalid || (r_ANEable^i_ANEnable))
r8_State <= stAN_ENABLE;
else
case(r8_State)
stAN_ENABLE : if(i_ANEnable) r8_State <= stAN_RESTART; else r8_State <= stAN_DIS_LINKOK;
stAN_RESTART : if(w_LinkTimerDone) r8_State <= stABILITY_DTECT;
stABILITY_DTECT : if(w_AbiMatch && r16_LpAdvAbility!=16'h0000) r8_State <= stACK_DTECT;
stACK_DTECT : if((w_AckMatch && (~r_ConsistencyMatch))||(w_AbiMatch && i16_RxConfigReg==16'h0000 && i_RUDIConfig))
r8_State <= stAN_ENABLE;
else if(w_AckMatch && r_ConsistencyMatch)
r8_State <= stCMPLT_ACK;
stCMPLT_ACK : if(w_AbiMatch && r16_LpAdvAbility==16'h0000) r8_State <= stAN_ENABLE;
else if(w_LinkTimerDone && (~w_AbiMatch||(r16_LpAdvAbility!=16'h0000)))
r8_State <= stIDLE_DTECT;
stIDLE_DTECT : if(w_IdleMatch && w_LinkTimerDone) r8_State <= stLINK_OK; else
if(w_IdleMatch && r16_LpAdvAbility==16'h0000) r8_State <= stAN_ENABLE;
stLINK_OK : if(w_AbiMatch) r8_State <= stAN_ENABLE;
stAN_DIS_LINKOK : r8_State <= stAN_DIS_LINKOK;
endcase
end
 
always@(posedge i_Clk or negedge i_ARst_L)
if(!i_ARst_L) begin
r16_LpAdvAbility <= 16'h0000;
o3_Xmit <= `cXmitIDLE;
r21_LinkTimer <= 21'h0;
o16_TxConfigReg <= 16'h0;
r2_IdleMatchCnt <= 2'b00;
r16_AbilityReg <= 16'h0;
end else begin
//Xmit
case(r8_State)
stAN_ENABLE : if(i_ANEnable) o3_Xmit <= `cXmitCONFIG; else o3_Xmit <= `cXmitIDLE;
stIDLE_DTECT: o3_Xmit <= `cXmitIDLE;
stLINK_OK : o3_Xmit <= `cXmitDATA;
stAN_DIS_LINKOK: o3_Xmit <= `cXmitDATA;
endcase
case(r8_State)
stAN_ENABLE: r21_LinkTimer <= 21'h0;
stAN_RESTART: if(w_LinkTimerDone==1'b0) r21_LinkTimer <= r21_LinkTimer+21'h1;
stACK_DTECT : r21_LinkTimer <= 21'h0;
stCMPLT_ACK : if(w_LinkTimerDone && (~w_AbiMatch||(r16_LpAdvAbility!=16'h0000))) r21_LinkTimer <= 21'h0; else
if(w_LinkTimerDone==1'b0) r21_LinkTimer <= r21_LinkTimer+21'h1;
stIDLE_DTECT: if(w_LinkTimerDone==1'b0) r21_LinkTimer <= r21_LinkTimer+21'h1;
stLINK_OK : r21_LinkTimer <= 21'h0;
endcase
case(r8_State)
stAN_ENABLE: if(i_ANEnable) o16_TxConfigReg <= 16'h0000;
stAN_RESTART: if(w_LinkTimerDone) begin
o16_TxConfigReg[15] <= i16_LcAdvAbility[16];
o16_TxConfigReg[14] <= 1'b0;
o16_TxConfigReg[13:0] <= i16_LcAdvAbility[14:1];
end
stACK_DTECT : o16_TxConfigReg[14] <= 1'b1;
endcase
if(r8_State==stABILITY_DTECT) r_ToggleTx <= i16_LcAdvAbility[12];
else if(r8_State==stCMPLT_ACK) r_ToggleTx <= ~r_ToggleTx;
if(r8_State==stCMPLT_ACK) r_ToggleRx<=i16_RxConfigReg[11];
//Sync Reset
if(r8_State==stAN_RESTART)
begin
r2_AbilityMatchCnt <= 2'b00;
r16_AbilityReg <= 16'h0;
r16_LpAdvAbility <= 16'h0;
r2_AcknowlMatchCnt <= 2'b00;
r_ConsistencyMatch <= 1'b0;
r2_IdleMatchCnt <= 2'b00;
end else
begin
//w_AbiMatch
if(i_RUDIIdle)
r2_AbilityMatchCnt <= 2'b00;
else if(i_RUDIConfig) begin
if(i16_RxConfigReg[13:00] == r16_LpAdvAbility[14:01] && i16_RxConfigReg[15]==r16_LpAdvAbility[16])
begin
if(r2_AbilityMatchCnt!=2'b11) r2_AbilityMatchCnt<=r2_AbilityMatchCnt+1;
end
else
r2_AbilityMatchCnt <= 2'b01;
end
if(r8_State==stABILITY_DTECT && w_AbiMatch && r16_LpAdvAbility!=16'h00) r16_AbilityReg <= r16_LpAdvAbility;
//Ack Match
if(i_RUDIIdle)
r2_AcknowlMatchCnt <= 2'b00;
else if(i_RUDIConfig) begin
if(i16_RxConfigReg[15:00] == r16_LpAdvAbility[16:01] && (i16_RxConfigReg[14]==1'b1))
begin
if(r2_AcknowlMatchCnt!=2'b11) r2_AcknowlMatchCnt<=r2_AcknowlMatchCnt+1;
//Consistency Match
//When the flag acknowledge match is about to be set
//If the bits are same as r16_AbilityReg , consistent
//Else Not consistent;
//Consistency match is set at the same time as Acknowledge match
if(r2_AcknowlMatchCnt==2'b10 && (i16_RxConfigReg[13:00] == r16_AbilityReg[13:00] && i16_RxConfigReg[15]==r16_AbilityReg[15]))
r_ConsistencyMatch <= 1'b1; else r_ConsistencyMatch<=1'b0;
end
else
r2_AcknowlMatchCnt <= 2'b01;
end
if(i_RUDIConfig)
r16_LpAdvAbility <= i16_RxConfigReg;
if(i_RUDIIdle) r2_IdleMatchCnt <= r2_IdleMatchCnt+2'b01;
else if(i_RUDIConfig|i_RUDIInvalid) r2_IdleMatchCnt<=2'b00;
end
end
//synopsys synthesis_off
reg [239:0] r240_ANStateName;
always@(*)
case(r8_State)
stAN_ENABLE :r240_ANStateName<="stAN_ENABLE ";
stAN_RESTART :r240_ANStateName<="stAN_RESTART ";
stABILITY_DTECT :r240_ANStateName<="stABILITY_DTECT ";
stACK_DTECT :r240_ANStateName<="stACK_DTECT ";
stCMPLT_ACK :r240_ANStateName<="stCMPLT_ACK ";
stIDLE_DTECT :r240_ANStateName<="stIDLE_DTECT ";
stLINK_OK :r240_ANStateName<="stLINK_OK ";
stAN_DIS_LINKOK :r240_ANStateName<="stAN_DIS_LINKOK ";
endcase
//synopsys synthesis_on
endmodule
/src/mClkBuf.v
0,0 → 1,15
/*
Developed By Subtleware Corporation Pte Ltd 2011
File :
Description :
Remarks :
Revision :
Date Author Description
02/09/12 Jefflieu
*/
 
module mClkBuf(input i_Clk,output o_Clk);
 
assign o_Clk = i_Clk;
endmodule
/src/mRegisters.v
0,0 → 1,147
/*
Developed By Subtleware Corporation Pte Ltd 2011
File :
Description :
Remarks :
Revision :
Date Author Description
02/09/12 Jefflieu
*/
`timescale 1ns/100ps
`include "SGMIIDefs.v"
module mRegisters(
input w_ARstLogic_L,
input i_Clk,
input i_Cyc,
input i_Stb,
input i_WEn,
input [07:00] i8_Addr,
input [31:00] i32_WrData,
output reg [31:00] o32_RdData,
output reg o_Ack,
output o_Stall,
inout io_Mdio,
input i_Mdc,
//This is used in Phy-Side SGMII
input i_PhyLink,
input i_PhyDuplex,
input [1:0] i2_PhySpeed,
//MAC-Side Speed,
output [01:00] o2_SGMIISpeed,
//MAC-Side Duplex,
output o_SGMIIDuplex,
//Register in and out,
output [20:00] o21_LinkTimer,
input [02:00] i3_XmitState,
input [15:00] i16_TxConfigReg,
output o_MIIRst_L,
output o_ANEnable,
output o_ANRestart,
output o_Loopback,
output o_GXBPowerDown,
output [15:00] o16_LcAdvAbility,
input i_ANComplete,
input i_SyncStatus,
input [15:00] i16_LpAdvAbility);
//TODO: Local BUs interface to setup registers
//Register Write
wire w_Write;
reg r_Write;
wire w_WritePulse;
wire [04:00] w5_Addr;
wire [15:00] w16_WrData;
reg [15:00] r16_CtrlReg0;
reg [15:00] r16_CtrlReg4;
wire [15:00] w16_StatusReg1;
reg [15:00] r16_ModeReg;
wire [15:00] w16_LcAdvAbility;
wire w_UseAsSGMII;
reg r_Read;
wire w_Read;
wire w_ReadPulse;
wire w_SGMII_PHY;
reg [20:00] r21_LinkTimer;
reg [15:00] r16_ScratchRev;
wire w_UseLcConfig;
assign o21_LinkTimer = r21_LinkTimer;
assign w5_Addr = i8_Addr[6:2];
assign w16_WrData = i32_WrData[15:00];
assign w_Write = (i_Cyc & i_Stb & i_WEn);
assign w_WritePulse = w_Write & (~r_Write);
assign w_Read = (i_Cyc & i_Stb & (~i_WEn));
assign w_ReadPulse = w_Read & (~r_Read);
assign o_Stall = (w_Write|w_Read)&(~o_Ack);
always@(posedge i_Clk or negedge w_ARstLogic_L)
if(w_ARstLogic_L==1'b0)
begin
r16_CtrlReg4 <= `cReg4Default;
r16_CtrlReg0 <= `cReg0Default;
r16_ModeReg <= `cRegXDefault;
r21_LinkTimer <= `cRegLinkTimerDefault;
r16_ScratchRev <= 16'h1_0_00;
end
else
begin
//Write Controller
r_Write <= w_Write;
o_Ack <= w_WritePulse|w_ReadPulse;
//Control Register 0
if(w_WritePulse && w5_Addr==5'b00000) r16_CtrlReg0 <= w16_WrData;
else begin
if(i3_XmitState==`cXmitCONFIG) r16_CtrlReg0[9] <= 1'b0;
r16_CtrlReg0[15] <= 1'b0;
end
if(w_WritePulse && w5_Addr==5'b00100) r16_CtrlReg4 <= w16_WrData;
if(w_WritePulse && w5_Addr==5'b01000) r21_LinkTimer[15:00] <= w16_WrData;
if(w_WritePulse && w5_Addr==5'b01001) r21_LinkTimer[20:16] <= w16_WrData[4:0];
if(w_WritePulse && w5_Addr==5'b01010) r16_ScratchRev <= w16_WrData;
if(w_WritePulse && w5_Addr==5'b11111) r16_ModeReg <= w16_WrData;
//Read Controller
r_Read <= w_Read;
if(w_ReadPulse)
case(w5_Addr)
5'h00: o32_RdData <= {16'h0,r16_CtrlReg0};
5'h01: o32_RdData <= {16'h0,w16_StatusReg1};
5'h02: o32_RdData <= 32'h0;
5'h03: o32_RdData <= 32'h0;
5'h04: o32_RdData <= {16'h0,w16_LcAdvAbility};
5'h05: o32_RdData <= {16'h0,i16_LpAdvAbility};
5'h08: o32_RdData <= {16'h0,r21_LinkTimer[15:00]};
5'h09: o32_RdData <= {16'h0,11'h0,r21_LinkTimer[20:16]};
5'h0A: o32_RdData <= r16_ScratchRev;
5'h1F: o32_RdData <= r16_ModeReg;
default: o32_RdData <= 32'h0;
endcase
end
assign o_ANRestart = r16_CtrlReg0[9];
assign o_MIIRst_L = ~r16_CtrlReg0[15];
assign o_ANEnable = r16_CtrlReg0[12];
assign o_Loopback = r16_CtrlReg0[14];
assign o_GxBPowerDown = r16_CtrlReg0[11];
assign o16_LcAdvAbility = w16_LcAdvAbility;
assign w16_LcAdvAbility = (w_UseAsSGMII==1'b0)?({1'b0,i16_TxConfigReg[15],r16_CtrlReg4[13:12],3'b000,r16_CtrlReg4[8:7],2'b01,5'b00000})://1000-X mode
((w_SGMII_PHY==1'b1)?({i_PhyLink,i16_TxConfigReg[15],1'b0,i_PhyDuplex,i2_PhySpeed,10'h1}):
({1'b0,i16_TxConfigReg[15],1'b0,3'b000,10'h1}));//SGMII mode - MAC Side
assign w16_StatusReg1 = {9'h0,i_ANComplete,2'b01,i_SyncStatus,2'b0};
assign w_UseAsSGMII = r16_ModeReg[0];
assign w_SGMII_PHY = r16_ModeReg[1];
assign w_UseLcConfig = r16_ModeReg[2];
assign o2_SGMIISpeed = (w_UseAsSGMII==1'b0)?2'b10:((w_UseLcConfig==1'b0)?i16_LpAdvAbility[11:10]:{r16_CtrlReg0[6],r16_CtrlReg0[13]});
assign o_SGMIIDuplex = (w_UseAsSGMII==1'b0)?1'b1:((w_UseLcConfig==1'b0)?i16_LpAdvAbility[12]:{r16_CtrlReg0[8]});
 
endmodule
/src/mXcver.v
0,0 → 1,82
/*
Developed By Subtleware Corporation Pte Ltd 2011
File :
Description :
Remarks :
Revision :
Date Author Description
*/
 
module mXcver #(parameter pXcverName="AltCycIV") (
 
input i_SerRx,
output o_SerTx,
input i_RefClk125M,
output o_TxClk,
input i_CalClk,
input i_GxBPwrDwn,
input i_XcverDigitalRst,
output o_PllLocked,
output o_SignalDetect,
output [07:00] o8_RxCodeGroup,
output o_RxCodeInvalid,
output o_RxCodeCtrl,
input [07:00] i8_TxCodeGroup,
input i_TxCodeValid,
input i_TxCodeCtrl,
input i_TxForceNegDisp,
output o_RunningDisparity);
 
 
 
generate
if(pXcverName=="AltCycIV")
wire [04:00] w5_ReconfigFromGxb;
wire [03:00] w4_ReconfigToGxb;
wire w_Reconfiguring;
begin:AltCycIVXcver
mAltGX u0AltGX (
.cal_blk_clk (i_CalClk),
.gxb_powerdown (i_GxBPwrDwn),
.pll_inclk (i_RefClk125M),
.reconfig_clk (i_CalClk),
.reconfig_togxb (w4_ReconfigToGxb),
.rx_analogreset (1'b0),
.pll_locked (o_PllLocked),
.reconfig_fromgxb (w5_ReconfigFromGxb),
.rx_digitalreset (i_XcverDigitalRst),
.rx_datain (i_SerRx),
.tx_dataout (o_SerTx),
.tx_ctrlenable (i_TxCodeCtrl),
.tx_datain (i8_TxCodeGroup),
.tx_digitalreset (i_XcverDigitalRst),
.rx_errdetect (o_RxCodeInvalid),
.rx_ctrldetect (o_RxCodeCtrl),
.rx_dataout (o8_RxCodeGroup),
.rx_disperr (),
.rx_patterndetect (),
.rx_rlv (),
.rx_syncstatus (o_SignalDetect),
.tx_clkout (o_TxClk));
assign o_RunningDisparity = 1'b0;
mAltGXReconfig u0AltGXReconfig(
.reconfig_clk (i_CalClk),
.reconfig_fromgxb (w5_ReconfigFromGxb),
.busy (w_Reconfiguring),
.reconfig_togxb (w4_ReconfigToGxb));
end
endgenerate
 
endmodule
/src/mSGMII.v
0,0 → 1,388
/*
Developed By Subtleware Corporation Pte Ltd 2011
File :
Description :
This core implements:
B1000-X Standard
PCS/PMA of SGMII MAC Side
Remarks :
Revision :
Date Author Description
02/09/12 Jefflieu
*/
 
`timescale 1ns/10ps
`include "SGMIIDefs.v"
 
module mSGMII
(
//Tranceiver Interface
input i_SerRx,
output o_SerTx,
input i_CalClk,
input i_RefClk125M,
input i_ARstHardware_L,
 
//Local BUS interface
//Wishbonebus, single transaction mode (non-pipeline slave)
input i_Cyc,
input i_Stb,
input i_WEn,
input [31:00] i32_WrData,
input [07:00] iv_Addr,
output [31:00] o32_RdData,
output o_Ack,
input i_Mdc,
inout io_Mdio,
output o_Linkup,
output o_ANDone,
output [1:0] o2_SGMIISpeed,
output o_SGMIIDuplex,
//GMII Interface
input [07:00] i8_TxD,
input i_TxEN,
input i_TxER,
output [07:00] o8_RxD,
output o_RxDV,
output o_RxER,
output o_GMIIClk,
output o_MIIClk,
output o_Col,
output o_Crs);
wire w_ClkSys;
wire w_Loopback;
reg r_RestartAN;
wire w_ANEnable;
wire [15:00] w16_Status;
wire w_MIIRst_L;
wire w_ANComplete;
wire [07:00] w8_RxCG_SyncToRxver;
wire w_RxCGInv_SyncToRxver;
wire w_RxCGCtrl_SyncToRxver;
wire w_SyncStatus,w_RxEven,w_IsComma,w_OSValid;
wire w_IsI1Set,w_IsI2Set,w_IsC1Set,w_IsC2Set,w_IsTSet,w_IsVSet,w_IsSSet,w_IsRSet;
wire w_Receiving;
wire w_Transmitting;
wire w_CheckEndKDK,w_CheckEndKD21_5D0_0,w_CheckEndKD2_2D0_0,w_CheckEndTRK,w_CheckEndTRR,w_CheckEndRRR,w_CheckEndRRK,w_CheckEndRRS;
reg r_CheckEndKDK,r_CheckEndKD21_5D0_0,r_CheckEndKD2_2D0_0,r_CheckEndTRK,r_CheckEndTRR,r_CheckEndRRR,r_CheckEndRRK,r_CheckEndRRS;
wire [2:0] w3_XmitState;
wire [16:01] w16_TxConfigReg;
wire [15:00] w16_RxConfigReg;
wire [15:00] w16_LcAdvAbility;
wire [15:00] w16_LpAdvAbility;
wire w_RUDIConfig;
wire w_RUDIIdle;
wire w_RUDIInvalid;
wire w_ARstLogic_L;
wire w_MIIReset_L;
wire w_ANRestart;
//This delay stage is for the function checkend
reg [07:00] r8_RxCodeGroup[0:2];
reg r_RxCgInvalid[0:2];
reg r_RxCgCtrl[0:2];
wire [2:0] w3_PreCheckIsSSet;
wire [2:0] w3_PreCheckIsTSet;
wire [2:0] w3_PreCheckIsRSet;
wire [2:0] w3_PreCheckIsComma;
wire [2:0] w3_PreCheckIsD21_5;
wire [2:0] w3_PreCheckIsD2_2;
wire [2:0] w3_PreCheckIsD;
wire [2:0] w3_PreCheckIsD0_0;
wire w_GxBPowerDown;
wire w_TxCodeCtrl, w_TxCodeValid, w_RxCodeInvalid, w_RxCodeCtrl;
wire [07:00] w8_TxCode, w8_RxCode;
wire w_SignalDetect;
wire w_TxForceNegDisp;
wire w_PllLocked;
wire [20:00] w21_LinkTimer;
wire w_TxEN,w_TxER,w_RxER, w_RxDV;
wire [07:00] w8_RxD, w8_TxD;
//MII Clock Gen
reg [6:0] r7_Cntr;
reg r_MIIClk;
reg r_MIIClk_D;
wire w_SamplingClk;
integer DELAY;
assign o_Linkup = w_SyncStatus;
assign o_ANDone = w_ANComplete;
mRateAdapter u0RateAdapter(
//MAC Side signal
.i_TxClk (o_MIIClk),
.i_TxEN (i_TxEN ),
.i_TxER (i_TxER ),
.i8_TxD (i8_TxD ),
.i_RxClk (o_MIIClk),
.o_RxEN (o_RxDV),
.o_RxER (o_RxER),
.o8_RxD (o8_RxD),
.i2_Speed (o2_SGMIISpeed),
//SGMII PHY side
.i_SamplingClk (w_SamplingClk),
.i_GClk (w_ClkSys),
.o_TxEN (w_TxEN),
.o_TxER (w_TxER),
.o8_TxD (w8_TxD),
.i_RxEN (w_RxDV),
.i_RxER (w_RxER),
.i8_RxD (w8_RxD));
generate
genvar STAGE;
for(STAGE=0;STAGE<3;STAGE=STAGE+1)
begin
assign w3_PreCheckIsComma[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b1 && r8_RxCodeGroup[STAGE]==`K28_5)?1'b1:1'b0;
assign w3_PreCheckIsTSet[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b1 && r8_RxCodeGroup[STAGE]==`K29_7)?1'b1:1'b0;
assign w3_PreCheckIsRSet[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b1 && r8_RxCodeGroup[STAGE]==`K23_7)?1'b1:1'b0;
assign w3_PreCheckIsD21_5[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b0 && r8_RxCodeGroup[STAGE]==`D21_5)?1'b1:1'b0;
assign w3_PreCheckIsD2_2[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b0 && r8_RxCodeGroup[STAGE]==`D2_2)?1'b1:1'b0;
assign w3_PreCheckIsD[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b0)?1'b1:1'b0;
assign w3_PreCheckIsD0_0[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b0 && r8_RxCodeGroup[STAGE]==`D0_0)?1'b1:1'b0;
assign w3_PreCheckIsSSet[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b1 && r8_RxCodeGroup[STAGE]==`K27_7)?1'b1:1'b0;
end
endgenerate
assign w_CheckEndKDK = w3_PreCheckIsComma[2] & w3_PreCheckIsD[1]&w3_PreCheckIsComma[0];
assign w_CheckEndRRR = &(w3_PreCheckIsRSet);
assign w_CheckEndTRK = w3_PreCheckIsTSet[2] & w3_PreCheckIsRSet[1] & w3_PreCheckIsComma[0];
assign w_CheckEndTRR = w3_PreCheckIsTSet[2] & w3_PreCheckIsRSet[1] & w3_PreCheckIsRSet[0];
assign w_CheckEndKD21_5D0_0 = w3_PreCheckIsComma[2] & w3_PreCheckIsD21_5[1] & w3_PreCheckIsD2_2[0];
assign w_CheckEndKD2_2D0_0 = w3_PreCheckIsComma[2] & w3_PreCheckIsD2_2[1] & w3_PreCheckIsD2_2[0];
assign w_CheckEndRRK = w3_PreCheckIsRSet[2] & w3_PreCheckIsRSet[1] & w3_PreCheckIsComma[0];
assign w_CheckEndRRS = w3_PreCheckIsRSet[2] & w3_PreCheckIsRSet[1] & w3_PreCheckIsSSet[0];
always@(posedge w_ClkSys)
begin
r8_RxCodeGroup[0] <= w8_RxCode;
r_RxCgCtrl[0] <= w_RxCodeCtrl;
r_RxCgInvalid[0] <= w_RxCodeInvalid;
for(DELAY=1;DELAY<3;DELAY=DELAY+1)
begin
r8_RxCodeGroup[DELAY] <= r8_RxCodeGroup[DELAY-1];
r_RxCgInvalid[DELAY] <= r_RxCgInvalid[DELAY-1];
r_RxCgCtrl[DELAY] <= r_RxCgCtrl[DELAY-1];
end
end
assign o_Col = w_Transmitting & w_Receiving;
assign o_Crs = 1'b0;
assign w_ARstLogic_L = w_PllLocked & i_ARstHardware_L & (w_MIIRst_L);
mRegisters u0Registers(
.w_ARstLogic_L (w_ARstLogic_L),
.i_Clk (w_ClkSys),
.i_Cyc (i_Cyc),
.i_Stb (i_Stb),
.i_WEn (i_WEn),
.i8_Addr (iv_Addr),
.i32_WrData (i32_WrData),
.o32_RdData (o32_RdData),
.o_Ack (o_Ack),
.o_Stall (o_Stall),
.io_Mdio (io_Mdio),
.i_Mdc (i_Mdc),
//Register in and out,
//MAC-Side SGMII
.o2_SGMIISpeed (o2_SGMIISpeed),
.o_SGMIIDuplex (o_SGMIIDuplex),
//Phy-Side SGMII
.i_PhyLink (i_PhyLink ),
.i_PhyDuplex (i_PhyDuplex),
.i2_PhySpeed (i2_PhySpeed),
.o21_LinkTimer (w21_LinkTimer),
.i16_TxConfigReg (w16_TxConfigReg),
.o_MIIRst_L (w_MIIRst_L),
.o_ANEnable (w_ANEnable),
.o_ANRestart (w_ANRestart),
.o_Loopback (w_Loopback),
.o_GXBPowerDown (w_GxBPowerDown),
.o16_LcAdvAbility (w16_LcAdvAbility),
.i3_XmitState (w3_XmitState),
.i_SyncStatus (w_SyncStatus),
.i_ANComplete (w_ANComplete),
.i16_LpAdvAbility (w16_LpAdvAbility));
mSyncCtrl u0SyncCtrl(
.i_Clk (w_ClkSys ),
.i_Cke ((~w_GxBPowerDown) ),
.i_ARst_L (w_ARstLogic_L ),
.i_CtrlLoopBack (w_Loopback ),
.i8_RxCodeGroupIn (r8_RxCodeGroup[2] ),
.i_RxCodeInvalid (r_RxCgInvalid[2] ),
.i_RxCodeCtrl (r_RxCgCtrl[2] ),
.i_SignalDetect (w_SignalDetect ),
.o8_RxCodeGroupOut (w8_RxCG_SyncToRxver ),
.o_RxCodeInvalid (w_RxCGInv_SyncToRxver ),
.o_RxCodeCtrl (w_RxCGCtrl_SyncToRxver ),
.o_RxEven (w_RxEven ),
.o_SyncStatus (w_SyncStatus ),
.o_BitSlip (),
.o_IsComma (w_IsComma ),
.o_OrderedSetValid (w_OSValid ),
.o_IsI1Set (w_IsI1Set ),
.o_IsI2Set (w_IsI2Set ),
.o_IsC1Set (w_IsC1Set ),
.o_IsC2Set (w_IsC2Set ),
.o_IsTSet (w_IsTSet ),
.o_IsVSet (w_IsVSet ),
.o_IsSSet (w_IsSSet ),
.o_IsRSet (w_IsRSet ));
always@(posedge w_ClkSys)
begin
r_CheckEndKDK <= w_CheckEndKDK;
r_CheckEndKD21_5D0_0 <= w_CheckEndKD21_5D0_0;
r_CheckEndKD2_2D0_0 <= w_CheckEndKD2_2D0_0;
r_CheckEndTRK <= w_CheckEndTRK;
r_CheckEndTRR <= w_CheckEndTRR;
r_CheckEndRRR <= w_CheckEndRRR;
r_CheckEndRRK <= w_CheckEndRRK;
r_CheckEndRRS <= w_CheckEndRRS;
end
mReceive u0Receive(
.i8_RxCodeGroupIn (w8_RxCG_SyncToRxver ),
.i_RxCodeInvalid (w_RxCGInv_SyncToRxver ),
.i_RxCodeCtrl (w_RxCGCtrl_SyncToRxver ),
.i_RxEven (w_RxEven ),
.i3_Xmit (w3_XmitState),
.i_IsComma (w_IsComma ),
.i_OrderedSetValid (w_OSValid ),
.i_IsI1Set (w_IsI1Set ),
.i_IsI2Set (w_IsI2Set ),
.i_IsC1Set (w_IsC1Set ),
.i_IsC2Set (w_IsC2Set ),
.i_IsTSet (w_IsTSet ),
.i_IsVSet (w_IsVSet ),
.i_IsSSet (w_IsSSet ),
.i_IsRSet (w_IsRSet ),
.i_CheckEndKDK (r_CheckEndKDK ),
.i_CheckEndKD21_5D0_0 (r_CheckEndKD21_5D0_0 ),
.i_CheckEndKD2_2D0_0 (r_CheckEndKD2_2D0_0 ),
.i_CheckEndTRK (r_CheckEndTRK ),
.i_CheckEndTRR (r_CheckEndTRR ),
.i_CheckEndRRR (r_CheckEndRRR ),
.i_CheckEndRRK (r_CheckEndRRK ),
.i_CheckEndRRS (r_CheckEndRRS ),
.o16_RxConfigReg (w16_RxConfigReg),
.o_RUDIConfig (w_RUDIConfig),
.o_RUDIIdle (w_RUDIIdle),
.o_RUDIInvalid (w_RUDIInvalid),
.o_RxDV (w_RxDV ),
.o_RxER (w_RxER ),
.o8_RxD (w8_RxD ),
.o_Invalid (o_Invalid),
.o_Receiving (w_Receiving),
.i_Clk (w_ClkSys),
.i_ARst_L (w_ARstLogic_L));
mANCtrl u0ANCtrl(
.i_Clk (w_ClkSys ),
.i_ARst_L (w_ARstLogic_L ),
.i_Cke ((~i_PwrDown) ),
.i_RestartAN (w_ANRestart ),
.i_SyncStatus (w_SyncStatus ),
.i_ANEnable (w_ANEnable ),
.i21_LinkTimer (w21_LinkTimer ),
.i16_LcAdvAbility (w16_LcAdvAbility ),
.o16_LpAdvAbility (w16_LpAdvAbility ),
.o_ANComplete (w_ANComplete ),
.i16_RxConfigReg (w16_RxConfigReg ),
.i_RUDIConfig (w_RUDIConfig ),
.i_RUDIIdle (w_RUDIIdle ),
.i_RUDIInvalid (w_RUDIInvalid ),
.o3_Xmit (w3_XmitState ),
.o16_TxConfigReg (w16_TxConfigReg ));
mTransmit u0Transmit(
.i3_Xmit (w3_XmitState ),
.i16_ConfigReg (w16_TxConfigReg ),
.i_TxEN (w_TxEN ),
.i_TxER (w_TxER ),
.i8_TxD (w8_TxD ),
.o_Xmitting (w_Transmitting ),
.o_TxEven (w_TxEven ),
.o8_TxCodeGroupOut (w8_TxCode ),
.o_TxCodeValid (w_TxCodeValid ),
.o_TxCodeCtrl (w_TxCodeCtrl ),
.i_CurrentParity (w_CurrentParity ),
.i_Clk (w_ClkSys ),
.i_ARst_L (w_ARstLogic_L ));
mXcver u0Xcver(
 
.i_SerRx (i_SerRx ),
.o_SerTx (o_SerTx ),
.i_RefClk125M (i_RefClk125M ),
.o_TxClk (w_ClkSys ),
.i_CalClk (i_CalClk ),
.i_GxBPwrDwn (w_GxBPowerDown ),
.i_XcverDigitalRst (~w_ARstLogic_L ),
.o_PllLocked (w_PllLocked ),
.o_SignalDetect (w_SignalDetect ),
.o8_RxCodeGroup (w8_RxCode ),
.o_RxCodeInvalid (w_RxCodeInvalid ),
.o_RxCodeCtrl (w_RxCodeCtrl ),
.i8_TxCodeGroup (w8_TxCode ),
.i_TxCodeValid (w_TxCodeValid ),
.i_TxCodeCtrl (w_TxCodeCtrl ),
.i_TxForceNegDisp (w_TxForceNegDisp ),
.o_RunningDisparity (w_CurrentParity));
assign o_GMIIClk = w_ClkSys;
always@(posedge w_ClkSys)
begin
if(o2_SGMIISpeed==2'b01)
begin
if(r7_Cntr==7'h4) r7_Cntr<=7'h0; else r7_Cntr<=r7_Cntr+7'h1;
if(r7_Cntr==7'h4) r_MIIClk<=1'b1; else if(r7_Cntr==7'h1) r_MIIClk<=1'b0;
end
else if(o2_SGMIISpeed==2'b00)
begin
if(r7_Cntr==7'h49) r7_Cntr<=7'h0; else r7_Cntr<=r7_Cntr+7'h1;
if(r7_Cntr==7'h49) r_MIIClk<=1'b1; else if(r7_Cntr==7'h24) r_MIIClk<=1'b0;
end
r_MIIClk_D <= r_MIIClk;
end
assign w_SamplingClk = (r_MIIClk_D & (~r_MIIClk));
//Insert Clock Buffer or PLL if necessary
mClkBuf u0ClkBuf(.i_Clk(r_MIIClk),.o_Clk(o_MIIClk));
 
endmodule
 
 
 
 
 
/src/mAltGX/mAltGX.v
0,0 → 1,1215
// megafunction wizard: %ALTGX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: alt_c3gxb
 
// ============================================================
// File Name: mAltGX.v
// Megafunction Name(s):
// alt_c3gxb
//
// Simulation Library Files(s):
// altera_mf;cycloneiv_hssi
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
 
 
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
 
 
//alt_c3gxb CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone IV GX" effective_data_rate="1250.0 Mbps" equalization_setting=1 equalizer_dcgain_setting=0 gxb_powerdown_width=1 loopback_mode="none" number_of_channels=1 number_of_quads=1 operation_mode="duplex" pll_bandwidth_type="auto" pll_control_width=1 pll_divide_by="1" pll_inclk_period=8000 pll_multiply_by="5" pll_pfd_fb_mode="internal" preemphasis_ctrl_1stposttap_setting=0 protocol="gige" receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=0 reconfig_pll_control_width=1 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="false" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_channel_width=8 rx_common_mode="0.82v" rx_datapath_protocol="basic" rx_deskew_pattern="0" rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_second_order_loop="false" rx_enable_self_test_mode="false" rx_force_signal_detect="true" rx_loop_1_digital_filter=8 rx_ppmselect=8 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="10100010010101111100" rx_rate_match_pattern2="10101011011010000011" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_signal_detect_loss_threshold=1 rx_signal_detect_threshold=8 rx_signal_detect_valid_threshold=14 rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="false" rx_use_external_termination="false" rx_word_aligner_num_byte=1 starting_channel_number=0 top_module_name="mAltGX" transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_bitslip_enable="false" tx_channel_width=8 tx_clkout_width=1 tx_common_mode="0.65v" tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_slew_rate="medium" tx_transmit_protocol="basic" tx_use_coreclk="false" tx_use_double_data_mode="false" tx_use_external_termination="false" use_calibration_block="true" vod_ctrl_setting=4 cal_blk_clk gxb_powerdown pll_inclk pll_locked reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_disperr rx_errdetect rx_patterndetect rx_rlv rx_syncstatus tx_clkout tx_ctrlenable tx_datain tx_dataout tx_digitalreset intended_device_family="Cyclone IV GX"
//VERSION_BEGIN 11.0 cbx_alt_c3gxb 2011:04:27:21:07:19:SJ cbx_altclkbuf 2011:04:27:21:07:19:SJ cbx_altiobuf_bidir 2011:04:27:21:07:19:SJ cbx_altiobuf_in 2011:04:27:21:07:19:SJ cbx_altiobuf_out 2011:04:27:21:07:19:SJ cbx_altpll 2011:04:27:21:07:19:SJ cbx_cycloneii 2011:04:27:21:07:19:SJ cbx_lpm_add_sub 2011:04:27:21:07:19:SJ cbx_lpm_compare 2011:04:27:21:07:19:SJ cbx_lpm_decode 2011:04:27:21:07:19:SJ cbx_lpm_mux 2011:04:27:21:07:19:SJ cbx_mgl 2011:04:27:21:11:03:SJ cbx_stingray 2011:04:27:21:07:19:SJ cbx_stratix 2011:04:27:21:07:19:SJ cbx_stratixii 2011:04:27:21:07:19:SJ cbx_stratixiii 2011:04:27:21:07:19:SJ cbx_stratixv 2011:04:27:21:07:19:SJ cbx_util_mgl 2011:04:27:21:07:19:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
 
 
//synthesis_resources = altpll 1 cycloneiv_hssi_calibration_block 1 cycloneiv_hssi_cmu 1 cycloneiv_hssi_rx_pcs 1 cycloneiv_hssi_rx_pma 1 cycloneiv_hssi_tx_pcs 1 cycloneiv_hssi_tx_pma 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module mAltGX_alt_c3gxb
(
cal_blk_clk,
gxb_powerdown,
pll_inclk,
pll_locked,
reconfig_clk,
reconfig_fromgxb,
reconfig_togxb,
rx_analogreset,
rx_ctrldetect,
rx_datain,
rx_dataout,
rx_digitalreset,
rx_disperr,
rx_errdetect,
rx_patterndetect,
rx_rlv,
rx_syncstatus,
tx_clkout,
tx_ctrlenable,
tx_datain,
tx_dataout,
tx_digitalreset) ;
input cal_blk_clk;
input [0:0] gxb_powerdown;
input [0:0] pll_inclk;
output [0:0] pll_locked;
input reconfig_clk;
output [4:0] reconfig_fromgxb;
input [3:0] reconfig_togxb;
input [0:0] rx_analogreset;
output [0:0] rx_ctrldetect;
input [0:0] rx_datain;
output [7:0] rx_dataout;
input [0:0] rx_digitalreset;
output [0:0] rx_disperr;
output [0:0] rx_errdetect;
output [0:0] rx_patterndetect;
output [0:0] rx_rlv;
output [0:0] rx_syncstatus;
output [0:0] tx_clkout;
input [0:0] tx_ctrlenable;
input [7:0] tx_datain;
output [0:0] tx_dataout;
input [0:0] tx_digitalreset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 cal_blk_clk;
tri0 [0:0] gxb_powerdown;
tri0 reconfig_clk;
tri0 [0:0] rx_analogreset;
tri0 [0:0] rx_digitalreset;
tri0 [0:0] tx_ctrlenable;
tri0 [7:0] tx_datain;
tri0 [0:0] tx_digitalreset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
 
 
parameter starting_channel_number = 0;
 
 
wire [5:0] wire_pll0_clk;
wire wire_pll0_fref;
wire wire_pll0_icdrclk;
wire wire_pll0_locked;
wire wire_cal_blk0_nonusertocmu;
wire wire_cent_unit0_dpriodisableout;
wire wire_cent_unit0_dprioout;
wire wire_cent_unit0_quadresetout;
wire [3:0] wire_cent_unit0_rxanalogresetout;
wire [3:0] wire_cent_unit0_rxcrupowerdown;
wire [3:0] wire_cent_unit0_rxdigitalresetout;
wire [3:0] wire_cent_unit0_rxibpowerdown;
wire [1599:0] wire_cent_unit0_rxpcsdprioout;
wire [1199:0] wire_cent_unit0_rxpmadprioout;
wire [3:0] wire_cent_unit0_txanalogresetout;
wire [3:0] wire_cent_unit0_txdetectrxpowerdown;
wire [3:0] wire_cent_unit0_txdigitalresetout;
wire [3:0] wire_cent_unit0_txdividerpowerdown;
wire [3:0] wire_cent_unit0_txobpowerdown;
wire [599:0] wire_cent_unit0_txpcsdprioout;
wire [1199:0] wire_cent_unit0_txpmadprioout;
wire wire_receive_pcs0_cdrctrllocktorefclkout;
wire [1:0] wire_receive_pcs0_ctrldetect;
wire [19:0] wire_receive_pcs0_dataout;
wire [1:0] wire_receive_pcs0_disperr;
wire [399:0] wire_receive_pcs0_dprioout;
wire [1:0] wire_receive_pcs0_errdetect;
wire [1:0] wire_receive_pcs0_patterndetect;
wire wire_receive_pcs0_rlv;
wire [1:0] wire_receive_pcs0_syncstatus;
wire [7:0] wire_receive_pma0_analogtestbus;
wire wire_receive_pma0_clockout;
wire wire_receive_pma0_diagnosticlpbkout;
wire [299:0] wire_receive_pma0_dprioout;
wire wire_receive_pma0_locktorefout;
wire [9:0] wire_receive_pma0_recoverdataout;
wire wire_receive_pma0_reverselpbkout;
wire wire_receive_pma0_signaldetect;
wire wire_transmit_pcs0_clkout;
wire [9:0] wire_transmit_pcs0_dataout;
wire [149:0] wire_transmit_pcs0_dprioout;
wire wire_transmit_pcs0_txdetectrx;
wire wire_transmit_pma0_clockout;
wire wire_transmit_pma0_dataout;
wire [299:0] wire_transmit_pma0_dprioout;
wire wire_transmit_pma0_seriallpbkout;
wire cal_blk_powerdown;
wire [0:0] cent_unit_quadresetout;
wire [3:0] cent_unit_rxcrupowerdn;
wire [3:0] cent_unit_rxibpowerdn;
wire [1599:0] cent_unit_rxpcsdprioin;
wire [1599:0] cent_unit_rxpcsdprioout;
wire [1199:0] cent_unit_rxpmadprioin;
wire [1199:0] cent_unit_rxpmadprioout;
wire [599:0] cent_unit_tx_dprioin;
wire [3:0] cent_unit_txdetectrxpowerdn;
wire [3:0] cent_unit_txdividerpowerdown;
wire [599:0] cent_unit_txdprioout;
wire [3:0] cent_unit_txobpowerdn;
wire [1199:0] cent_unit_txpmadprioin;
wire [1199:0] cent_unit_txpmadprioout;
wire [3:0] fixedclk_to_cmu;
wire [0:0] nonusertocmu_out;
wire [0:0] pll_areset;
wire [0:0] pll_powerdown;
wire [0:0] reconfig_togxb_busy;
wire [0:0] reconfig_togxb_disable;
wire [0:0] reconfig_togxb_in;
wire [0:0] reconfig_togxb_load;
wire [3:0] rx_analogreset_in;
wire [3:0] rx_analogreset_out;
wire [0:0] rx_coreclk_in;
wire [0:0] rx_deserclock_in;
wire [3:0] rx_digitalreset_in;
wire [3:0] rx_digitalreset_out;
wire [0:0] rx_enapatternalign;
wire [0:0] rx_locktodata;
wire [0:0] rx_locktorefclk;
wire [0:0] rx_locktorefclk_wire;
wire [7:0] rx_out_wire;
wire [1599:0] rx_pcsdprioin_wire;
wire [1599:0] rx_pcsdprioout;
wire [0:0] rx_phfifordenable;
wire [0:0] rx_phfiforeset;
wire [0:0] rx_phfifowrdisable;
wire [0:0] rx_pll_pfdrefclkout_wire;
wire [4:0] rx_pma_analogtestbus;
wire [0:0] rx_pma_clockout;
wire [9:0] rx_pma_recoverdataout_wire;
wire [1199:0] rx_pmadprioin_wire;
wire [1199:0] rx_pmadprioout;
wire [0:0] rx_powerdown;
wire [3:0] rx_powerdown_in;
wire [0:0] rx_prbscidenable;
wire [0:0] rx_reverselpbkout;
wire [0:0] rx_rmfiforeset;
wire [0:0] rx_signaldetect_wire;
wire [3:0] tx_analogreset_out;
wire [0:0] tx_clkout_int_wire;
wire [0:0] tx_core_clkout_wire;
wire [0:0] tx_coreclk_in;
wire [7:0] tx_datain_wire;
wire [9:0] tx_dataout_pcs_to_pma;
wire [0:0] tx_diagnosticlpbkin;
wire [3:0] tx_digitalreset_in;
wire [3:0] tx_digitalreset_out;
wire [599:0] tx_dprioin_wire;
wire [0:0] tx_forcedisp_wire;
wire [0:0] tx_invpolarity;
wire [0:0] tx_localrefclk;
wire [0:0] tx_phfiforeset;
wire [0:0] tx_pma_fastrefclk0in;
wire [0:0] tx_pma_refclk0in;
wire [0:0] tx_pma_refclk0inpulse;
wire [1199:0] tx_pmadprioin_wire;
wire [1199:0] tx_pmadprioout;
wire [0:0] tx_serialloopbackout;
wire [599:0] tx_txdprioout;
wire [0:0] txdataout;
wire [0:0] txdetectrxout;
wire [0:0] w_cent_unit_dpriodisableout1w;
 
altpll pll0
(
.activeclock(),
.areset((pll_areset[0] | pll_powerdown[0])),
.clk(wire_pll0_clk),
.clkbad(),
.clkloss(),
.enable0(),
.enable1(),
.extclk(),
.fbout(),
.fref(wire_pll0_fref),
.icdrclk(wire_pll0_icdrclk),
.inclk({{1{1'b0}}, pll_inclk[0]}),
.locked(wire_pll0_locked),
.phasedone(),
.scandataout(),
.scandone(),
.sclkout0(),
.sclkout1(),
.vcooverrange(),
.vcounderrange()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clkena({6{1'b1}}),
.clkswitch(1'b0),
.configupdate(1'b0),
.extclkena({4{1'b1}}),
.fbin(1'b1),
.pfdena(1'b1),
.phasecounterselect({4{1'b1}}),
.phasestep(1'b1),
.phaseupdown(1'b1),
.pllena(1'b1),
.scanaclr(1'b0),
.scanclk(1'b0),
.scanclkena(1'b1),
.scandata(1'b0),
.scanread(1'b0),
.scanwrite(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pll0.bandwidth_type = "AUTO",
pll0.clk0_divide_by = 1,
pll0.clk0_multiply_by = 5,
pll0.clk1_divide_by = 5,
pll0.clk1_multiply_by = 5,
pll0.clk2_divide_by = 5,
pll0.clk2_duty_cycle = 20,
pll0.clk2_multiply_by = 5,
pll0.dpa_divide_by = 1,
pll0.dpa_multiply_by = 5,
pll0.inclk0_input_frequency = 8000,
pll0.operation_mode = "no_compensation",
pll0.intended_device_family = "Cyclone IV GX",
pll0.lpm_type = "altpll";
cycloneiv_hssi_calibration_block cal_blk0
(
.calibrationstatus(),
.clk(cal_blk_clk),
.nonusertocmu(wire_cal_blk0_nonusertocmu),
.powerdn(cal_blk_powerdown)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.testctrl(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
cycloneiv_hssi_cmu cent_unit0
(
.adet({4{1'b0}}),
.alignstatus(),
.coreclkout(),
.digitaltestout(),
.dpclk(reconfig_clk),
.dpriodisable(reconfig_togxb_disable),
.dpriodisableout(wire_cent_unit0_dpriodisableout),
.dprioin(reconfig_togxb_in),
.dprioload(reconfig_togxb_load),
.dpriooe(),
.dprioout(wire_cent_unit0_dprioout),
.enabledeskew(),
.fiforesetrd(),
.fixedclk({{3{1'b0}}, fixedclk_to_cmu[0]}),
.nonuserfromcal(nonusertocmu_out[0]),
.quadreset(gxb_powerdown[0]),
.quadresetout(wire_cent_unit0_quadresetout),
.rdalign({4{1'b0}}),
.rdenablesync(1'b0),
.recovclk(1'b0),
.refclkout(),
.rxanalogreset({rx_analogreset_in[3:0]}),
.rxanalogresetout(wire_cent_unit0_rxanalogresetout),
.rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
.rxctrl({4{1'b0}}),
.rxctrlout(),
.rxdatain({32{1'b0}}),
.rxdataout(),
.rxdatavalid({4{1'b0}}),
.rxdigitalreset({rx_digitalreset_in[3:0]}),
.rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
.rxibpowerdown(wire_cent_unit0_rxibpowerdown),
.rxpcsdprioin({cent_unit_rxpcsdprioin[1599:0]}),
.rxpcsdprioout(wire_cent_unit0_rxpcsdprioout),
.rxphfifox4byteselout(),
.rxphfifox4rdenableout(),
.rxphfifox4wrclkout(),
.rxphfifox4wrenableout(),
.rxpmadprioin({cent_unit_rxpmadprioin[1199:0]}),
.rxpmadprioout(wire_cent_unit0_rxpmadprioout),
.rxpowerdown({rx_powerdown_in[3:0]}),
.rxrunningdisp({4{1'b0}}),
.syncstatus({4{1'b0}}),
.testout(),
.txanalogresetout(wire_cent_unit0_txanalogresetout),
.txctrl({4{1'b0}}),
.txctrlout(),
.txdatain({32{1'b0}}),
.txdataout(),
.txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
.txdigitalreset({tx_digitalreset_in[3:0]}),
.txdigitalresetout(wire_cent_unit0_txdigitalresetout),
.txdividerpowerdown(wire_cent_unit0_txdividerpowerdown),
.txobpowerdown(wire_cent_unit0_txobpowerdown),
.txpcsdprioin({cent_unit_tx_dprioin[599:0]}),
.txpcsdprioout(wire_cent_unit0_txpcsdprioout),
.txphfifox4byteselout(),
.txphfifox4rdclkout(),
.txphfifox4rdenableout(),
.txphfifox4wrenableout(),
.txpmadprioin({cent_unit_txpmadprioin[1199:0]}),
.txpmadprioout(wire_cent_unit0_txpmadprioout)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.pmacramtest(1'b0),
.refclkdig(1'b0),
.rxcoreclk(1'b0),
.rxphfifordenable(1'b1),
.rxphfiforeset(1'b0),
.rxphfifowrdisable(1'b0),
.scanclk(1'b0),
.scanmode(1'b0),
.scanshift(1'b0),
.testin({2000{1'b0}}),
.txclk(1'b0),
.txcoreclk(1'b0),
.txphfiforddisable(1'b0),
.txphfiforeset(1'b0),
.txphfifowrenable(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
cent_unit0.auto_spd_phystatus_notify_count = 0,
cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
cent_unit0.dprio_config_mode = 6'h01,
cent_unit0.in_xaui_mode = "false",
cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
cent_unit0.rx0_channel_bonding = "none",
cent_unit0.rx0_clk1_mux_select = "recovered clock",
cent_unit0.rx0_clk2_mux_select = "local reference clock",
cent_unit0.rx0_ph_fifo_reg_mode = "false",
cent_unit0.rx0_rd_clk_mux_select = "core clock",
cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
cent_unit0.rx0_use_double_data_mode = "false",
cent_unit0.tx0_channel_bonding = "none",
cent_unit0.tx0_rd_clk_mux_select = "central",
cent_unit0.tx0_reset_clock_output_during_digital_reset = "false",
cent_unit0.tx0_use_double_data_mode = "false",
cent_unit0.tx0_wr_clk_mux_select = "core_clk",
cent_unit0.use_coreclk_out_post_divider = "false",
cent_unit0.use_deskew_fifo = "false",
cent_unit0.lpm_type = "cycloneiv_hssi_cmu";
cycloneiv_hssi_rx_pcs receive_pcs0
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.bistdone(),
.bisterr(),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(),
.cdrctrllocktorefcl((reconfig_togxb_busy | rx_locktorefclk[0])),
.cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
.clkout(),
.coreclk(rx_coreclk_in[0]),
.coreclkout(),
.ctrldetect(wire_receive_pcs0_ctrldetect),
.datain(rx_pma_recoverdataout_wire[9:0]),
.dataout(wire_receive_pcs0_dataout),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[0]),
.disperr(wire_receive_pcs0_disperr),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pcsdprioin_wire[399:0]),
.dprioout(wire_receive_pcs0_dprioout),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[0]),
.errdetect(wire_receive_pcs0_errdetect),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.hipdataout(),
.hipdatavalid(),
.hipelecidle(),
.hipphydonestatus(),
.hipstatus(),
.invpol(1'b0),
.k1detect(),
.k2detect(),
.localrefclk(tx_localrefclk[0]),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(wire_receive_pcs0_patterndetect),
.phfifooverflow(),
.phfifordenable(rx_phfifordenable[0]),
.phfifordenableout(),
.phfiforeset(rx_phfiforeset[0]),
.phfiforesetout(),
.phfifounderflow(),
.phfifowrdisable(rx_phfifowrdisable[0]),
.phfifowrdisableout(),
.pipebufferstat(),
.pipedatavalid(),
.pipeelecidle(),
.pipephydonestatus(),
.pipepowerdown({2{1'b0}}),
.pipepowerstate({4{1'b0}}),
.pipestatetransdoneout(),
.pipestatus(),
.prbscidenable(rx_prbscidenable[0]),
.quadreset(cent_unit_quadresetout[0]),
.rdalign(),
.recoveredclk(rx_pma_clockout[0]),
.revbitorderwa(1'b0),
.revparallelfdbkdata(),
.rlv(wire_receive_pcs0_rlv),
.rmfifodatadeleted(),
.rmfifodatainserted(),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(rx_rmfiforeset[0]),
.rmfifowrena(1'b0),
.runningdisp(),
.rxdetectvalid(1'b0),
.rxfound({2{1'b0}}),
.signaldetect(),
.signaldetected(rx_signaldetect_wire[0]),
.syncstatus(wire_receive_pcs0_syncstatus),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslip(1'b0),
.elecidleinfersel({3{1'b0}}),
.grayelecidleinferselfromtx({3{1'b0}}),
.hip8b10binvpolarity(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hippowerdown({2{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrclk(1'b0),
.phfifox4wrenable(1'b0),
.pipe8b10binvpolarity(1'b0),
.pipeenrevparallellpbkfromtx(1'b0),
.pmatestbusin({8{1'b0}}),
.powerdn({2{1'b0}}),
.refclk(1'b0),
.revbyteorderwa(1'b0),
.wareset(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pcs0.align_pattern = "0101111100",
receive_pcs0.align_pattern_length = 10,
receive_pcs0.allow_align_polarity_inversion = "false",
receive_pcs0.allow_pipe_polarity_inversion = "false",
receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs0.auto_spd_phystatus_notify_count = 0,
receive_pcs0.bit_slip_enable = "false",
receive_pcs0.byte_order_mode = "none",
receive_pcs0.byte_order_pad_pattern = "0",
receive_pcs0.byte_order_pattern = "0",
receive_pcs0.byte_order_pld_ctrl_enable = "false",
receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs0.cdrctrl_enable = "false",
receive_pcs0.cdrctrl_mask_cycle = 800,
receive_pcs0.cdrctrl_min_lock_to_ref_cycle = 63,
receive_pcs0.cdrctrl_rxvalid_mask = "false",
receive_pcs0.channel_bonding = "none",
receive_pcs0.channel_number = ((starting_channel_number + 0) % 4),
receive_pcs0.channel_width = 8,
receive_pcs0.clk1_mux_select = "recovered clock",
receive_pcs0.clk2_mux_select = "local reference clock",
receive_pcs0.core_clock_0ppm = "false",
receive_pcs0.datapath_low_latency_mode = "false",
receive_pcs0.datapath_protocol = "basic",
receive_pcs0.dec_8b_10b_compatibility_mode = "true",
receive_pcs0.dec_8b_10b_mode = "normal",
receive_pcs0.deskew_pattern = "0",
receive_pcs0.disable_auto_idle_insertion = "true",
receive_pcs0.disable_running_disp_in_word_align = "false",
receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs0.dprio_config_mode = 6'h01,
receive_pcs0.elec_idle_infer_enable = "false",
receive_pcs0.elec_idle_num_com_detect = 3,
receive_pcs0.enable_bit_reversal = "false",
receive_pcs0.enable_self_test_mode = "false",
receive_pcs0.force_signal_detect_dig = "true",
receive_pcs0.hip_enable = "false",
receive_pcs0.infiniband_invalid_code = 0,
receive_pcs0.insert_pad_on_underflow = "false",
receive_pcs0.num_align_code_groups_in_ordered_set = 1,
receive_pcs0.num_align_cons_good_data = 4,
receive_pcs0.num_align_cons_pat = 3,
receive_pcs0.num_align_loss_sync_error = 4,
receive_pcs0.ph_fifo_low_latency_enable = "true",
receive_pcs0.ph_fifo_reg_mode = "false",
receive_pcs0.protocol_hint = "gige",
receive_pcs0.rate_match_back_to_back = "true",
receive_pcs0.rate_match_delete_threshold = 13,
receive_pcs0.rate_match_empty_threshold = 5,
receive_pcs0.rate_match_fifo_mode = "true",
receive_pcs0.rate_match_full_threshold = 20,
receive_pcs0.rate_match_insert_threshold = 11,
receive_pcs0.rate_match_ordered_set_based = "true",
receive_pcs0.rate_match_pattern1 = "10100010010101111100",
receive_pcs0.rate_match_pattern2 = "10101011011010000011",
receive_pcs0.rate_match_pattern_size = 20,
receive_pcs0.rate_match_reset_enable = "false",
receive_pcs0.rate_match_skip_set_based = "false",
receive_pcs0.rate_match_start_threshold = 7,
receive_pcs0.rd_clk_mux_select = "core clock",
receive_pcs0.recovered_clk_mux_select = "recovered clock",
receive_pcs0.run_length = 40,
receive_pcs0.run_length_enable = "true",
receive_pcs0.rx_detect_bypass = "false",
receive_pcs0.rx_phfifo_wait_cnt = 15,
receive_pcs0.rxstatus_error_report_mode = 0,
receive_pcs0.self_test_mode = "incremental",
receive_pcs0.use_alignment_state_machine = "true",
receive_pcs0.use_deskew_fifo = "false",
receive_pcs0.use_double_data_mode = "false",
receive_pcs0.use_parallel_loopback = "false",
receive_pcs0.lpm_type = "cycloneiv_hssi_rx_pcs";
cycloneiv_hssi_rx_pma receive_pma0
(
.analogtestbus(wire_receive_pma0_analogtestbus),
.clockout(wire_receive_pma0_clockout),
.crupowerdn(cent_unit_rxcrupowerdn[0]),
.datain(rx_datain[0]),
.datastrobeout(),
.deserclock(rx_deserclock_in[0]),
.diagnosticlpbkout(wire_receive_pma0_diagnosticlpbkout),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(rx_pmadprioin_wire[299:0]),
.dprioout(wire_receive_pma0_dprioout),
.freqlocked(),
.locktodata(((~ reconfig_togxb_busy) & rx_locktodata[0])),
.locktoref(rx_locktorefclk_wire[0]),
.locktorefout(wire_receive_pma0_locktorefout),
.powerdn(cent_unit_rxibpowerdn[0]),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
.recoverdataout(wire_receive_pma0_recoverdataout),
.reverselpbkout(wire_receive_pma0_reverselpbkout),
.rxpmareset(rx_analogreset_out[0]),
.seriallpbkin(tx_serialloopbackout[0]),
.signaldetect(wire_receive_pma0_signaldetect),
.testbussel(4'b0110)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dpashift(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pma0.allow_serial_loopback = "false",
receive_pma0.channel_number = ((starting_channel_number + 0) % 4),
receive_pma0.common_mode = "0.82V",
receive_pma0.deserialization_factor = 10,
receive_pma0.dprio_config_mode = 6'h01,
receive_pma0.effective_data_rate = "1250.0 Mbps",
receive_pma0.enable_local_divider = "false",
receive_pma0.enable_ltd = "false",
receive_pma0.enable_ltr = "false",
receive_pma0.enable_second_order_loop = "false",
receive_pma0.eq_dc_gain = 0,
receive_pma0.eq_setting = 1,
receive_pma0.force_signal_detect = "true",
receive_pma0.logical_channel_address = (starting_channel_number + 0),
receive_pma0.loop_1_digital_filter = 8,
receive_pma0.offset_cancellation = 1,
receive_pma0.ppm_gen1_2_xcnt_en = 1,
receive_pma0.ppm_post_eidle = 0,
receive_pma0.ppmselect = 8,
receive_pma0.protocol_hint = "gige",
receive_pma0.signal_detect_hysteresis = 8,
receive_pma0.signal_detect_hysteresis_valid_threshold = 14,
receive_pma0.signal_detect_loss_threshold = 1,
receive_pma0.termination = "OCT 100 Ohms",
receive_pma0.use_external_termination = "false",
receive_pma0.lpm_type = "cycloneiv_hssi_rx_pma";
cycloneiv_hssi_tx_pcs transmit_pcs0
(
.clkout(wire_transmit_pcs0_clkout),
.coreclk(tx_coreclk_in[0]),
.coreclkout(),
.ctrlenable({{1{1'b0}}, tx_ctrlenable[0]}),
.datain({{12{1'b0}}, tx_datain_wire[7:0]}),
.datainfull({22{1'b0}}),
.dataout(wire_transmit_pcs0_dataout),
.detectrxloop(1'b0),
.digitalreset(tx_digitalreset_out[0]),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_dprioin_wire[149:0]),
.dprioout(wire_transmit_pcs0_dprioout),
.enrevparallellpbk(1'b0),
.forcedisp({{1{1'b0}}, tx_forcedisp_wire[0]}),
.forceelecidleout(),
.grayelecidleinferselout(),
.hiptxclkout(),
.invpol(tx_invpolarity[0]),
.localrefclk(tx_localrefclk[0]),
.parallelfdbkout(),
.phfifooverflow(),
.phfiforddisable(1'b0),
.phfiforddisableout(),
.phfiforeset(tx_phfiforeset[0]),
.phfiforesetout(),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(),
.pipeenrevparallellpbkout(),
.pipepowerdownout(),
.pipepowerstateout(),
.pipestatetransdone(1'b0),
.powerdn({2{1'b0}}),
.quadreset(cent_unit_quadresetout[0]),
.rdenablesync(),
.revparallelfdbk({20{1'b0}}),
.txdetectrx(wire_transmit_pcs0_txdetectrx),
.xgmctrlenable(),
.xgmdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslipboundaryselect({5{1'b0}}),
.dispval({2{1'b0}}),
.elecidleinfersel({3{1'b0}}),
.forceelecidle(1'b0),
.hipdatain({10{1'b0}}),
.hipdetectrxloop(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hipforceelecidle(1'b0),
.hippowerdn({2{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdclk(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrenable(1'b0),
.pipetxswing(1'b0),
.prbscidenable(1'b0),
.refclk(1'b0),
.xgmctrl(1'b0),
.xgmdatain({8{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pcs0.allow_polarity_inversion = "false",
transmit_pcs0.bitslip_enable = "false",
transmit_pcs0.channel_bonding = "none",
transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4),
transmit_pcs0.channel_width = 8,
transmit_pcs0.core_clock_0ppm = "false",
transmit_pcs0.datapath_low_latency_mode = "false",
transmit_pcs0.datapath_protocol = "basic",
transmit_pcs0.disable_ph_low_latency_mode = "false",
transmit_pcs0.disparity_mode = "none",
transmit_pcs0.dprio_config_mode = 6'h01,
transmit_pcs0.elec_idle_delay = 6,
transmit_pcs0.enable_bit_reversal = "false",
transmit_pcs0.enable_idle_selection = "true",
transmit_pcs0.enable_reverse_parallel_loopback = "false",
transmit_pcs0.enable_self_test_mode = "false",
transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
transmit_pcs0.enc_8b_10b_mode = "normal",
transmit_pcs0.hip_enable = "false",
transmit_pcs0.ph_fifo_reg_mode = "false",
transmit_pcs0.prbs_cid_pattern = "false",
transmit_pcs0.protocol_hint = "gige",
transmit_pcs0.refclk_select = "local",
transmit_pcs0.self_test_mode = "incremental",
transmit_pcs0.use_double_data_mode = "false",
transmit_pcs0.wr_clk_mux_select = "core_clk",
transmit_pcs0.lpm_type = "cycloneiv_hssi_tx_pcs";
cycloneiv_hssi_tx_pma transmit_pma0
(
.cgbpowerdn(cent_unit_txdividerpowerdown[0]),
.clockout(wire_transmit_pma0_clockout),
.datain({tx_dataout_pcs_to_pma[9:0]}),
.dataout(wire_transmit_pma0_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
.diagnosticlpbkin(tx_diagnosticlpbkin[0]),
.dpriodisable(w_cent_unit_dpriodisableout1w[0]),
.dprioin(tx_pmadprioin_wire[299:0]),
.dprioout(wire_transmit_pma0_dprioout),
.fastrefclk0in(tx_pma_fastrefclk0in[0]),
.forceelecidle(1'b0),
.powerdn(cent_unit_txobpowerdn[0]),
.refclk0in(tx_pma_refclk0in[0]),
.refclk0inpulse(tx_pma_refclk0inpulse[0]),
.reverselpbkin(rx_reverselpbkout[0]),
.rxdetecten(txdetectrxout[0]),
.rxdetectvalidout(),
.rxfoundout(),
.seriallpbkout(wire_transmit_pma0_seriallpbkout),
.txpmareset(tx_analogreset_out[0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.rxdetectclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pma0.channel_number = ((starting_channel_number + 0) % 4),
transmit_pma0.common_mode = "0.65V",
transmit_pma0.dprio_config_mode = 6'h01,
transmit_pma0.effective_data_rate = "1250.0 Mbps",
transmit_pma0.enable_diagnostic_loopback = "false",
transmit_pma0.enable_reverse_serial_loopback = "false",
transmit_pma0.logical_channel_address = (starting_channel_number + 0),
transmit_pma0.preemp_tap_1 = 0,
transmit_pma0.protocol_hint = "gige",
transmit_pma0.rx_detect = 0,
transmit_pma0.serialization_factor = 10,
transmit_pma0.slew_rate = "medium",
transmit_pma0.termination = "OCT 100 Ohms",
transmit_pma0.use_external_termination = "false",
transmit_pma0.use_rx_detect = "false",
transmit_pma0.vod_selection = 4,
transmit_pma0.lpm_type = "cycloneiv_hssi_tx_pma";
assign
cal_blk_powerdown = 1'b0,
cent_unit_quadresetout = {wire_cent_unit0_quadresetout},
cent_unit_rxcrupowerdn = {wire_cent_unit0_rxcrupowerdown[3:0]},
cent_unit_rxibpowerdn = {wire_cent_unit0_rxibpowerdown[3:0]},
cent_unit_rxpcsdprioin = {{1200{1'b0}}, rx_pcsdprioout[399:0]},
cent_unit_rxpcsdprioout = {wire_cent_unit0_rxpcsdprioout[1599:0]},
cent_unit_rxpmadprioin = {{900{1'b0}}, rx_pmadprioout[299:0]},
cent_unit_rxpmadprioout = {wire_cent_unit0_rxpmadprioout[1199:0]},
cent_unit_tx_dprioin = {{450{1'b0}}, tx_txdprioout[149:0]},
cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[3:0]},
cent_unit_txdividerpowerdown = {wire_cent_unit0_txdividerpowerdown[3:0]},
cent_unit_txdprioout = {wire_cent_unit0_txpcsdprioout[599:0]},
cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[3:0]},
cent_unit_txpmadprioin = {{900{1'b0}}, tx_pmadprioout[299:0]},
cent_unit_txpmadprioout = {wire_cent_unit0_txpmadprioout[1199:0]},
fixedclk_to_cmu = {4{reconfig_clk}},
nonusertocmu_out = {wire_cal_blk0_nonusertocmu},
pll_areset = 1'b0,
pll_locked = {wire_pll0_locked},
pll_powerdown = 1'b0,
reconfig_fromgxb = {rx_pma_analogtestbus[4:1], wire_cent_unit0_dprioout},
reconfig_togxb_busy = reconfig_togxb[3],
reconfig_togxb_disable = reconfig_togxb[1],
reconfig_togxb_in = reconfig_togxb[0],
reconfig_togxb_load = reconfig_togxb[2],
rx_analogreset_in = {{3{1'b0}}, ((~ reconfig_togxb_busy) & rx_analogreset[0])},
rx_analogreset_out = {wire_cent_unit0_rxanalogresetout[3:0]},
rx_coreclk_in = {tx_core_clkout_wire[0]},
rx_ctrldetect = {wire_receive_pcs0_ctrldetect[0]},
rx_dataout = {rx_out_wire[7:0]},
rx_deserclock_in = {wire_pll0_icdrclk},
rx_digitalreset_in = {{3{1'b0}}, rx_digitalreset[0]},
rx_digitalreset_out = {wire_cent_unit0_rxdigitalresetout[3:0]},
rx_disperr = {wire_receive_pcs0_disperr[0]},
rx_enapatternalign = 1'b0,
rx_errdetect = {wire_receive_pcs0_errdetect[0]},
rx_locktodata = 1'b0,
rx_locktorefclk = 1'b0,
rx_locktorefclk_wire = {wire_receive_pcs0_cdrctrllocktorefclkout},
rx_out_wire = {wire_receive_pcs0_dataout[7:0]},
rx_patterndetect = {wire_receive_pcs0_patterndetect[0]},
rx_pcsdprioin_wire = {{1200{1'b0}}, cent_unit_rxpcsdprioout[399:0]},
rx_pcsdprioout = {{1200{1'b0}}, wire_receive_pcs0_dprioout},
rx_phfifordenable = 1'b1,
rx_phfiforeset = 1'b0,
rx_phfifowrdisable = 1'b0,
rx_pll_pfdrefclkout_wire = {wire_pll0_fref},
rx_pma_analogtestbus = {{4{1'b0}}, wire_receive_pma0_analogtestbus[6]},
rx_pma_clockout = {wire_receive_pma0_clockout},
rx_pma_recoverdataout_wire = {wire_receive_pma0_recoverdataout[9:0]},
rx_pmadprioin_wire = {{900{1'b0}}, cent_unit_rxpmadprioout[299:0]},
rx_pmadprioout = {{900{1'b0}}, wire_receive_pma0_dprioout},
rx_powerdown = 1'b0,
rx_powerdown_in = {{3{1'b0}}, rx_powerdown[0]},
rx_prbscidenable = 1'b0,
rx_reverselpbkout = {wire_receive_pma0_reverselpbkout},
rx_rlv = {wire_receive_pcs0_rlv},
rx_rmfiforeset = 1'b0,
rx_signaldetect_wire = {wire_receive_pma0_signaldetect},
rx_syncstatus = {wire_receive_pcs0_syncstatus[0]},
tx_analogreset_out = {wire_cent_unit0_txanalogresetout[3:0]},
tx_clkout = {tx_core_clkout_wire[0]},
tx_clkout_int_wire = {wire_transmit_pcs0_clkout},
tx_core_clkout_wire = {tx_clkout_int_wire[0]},
tx_coreclk_in = {tx_clkout_int_wire[0]},
tx_datain_wire = {tx_datain[7:0]},
tx_dataout = {txdataout[0]},
tx_dataout_pcs_to_pma = {wire_transmit_pcs0_dataout[9:0]},
tx_diagnosticlpbkin = {wire_receive_pma0_diagnosticlpbkout},
tx_digitalreset_in = {{3{1'b0}}, tx_digitalreset[0]},
tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout[3:0]},
tx_dprioin_wire = {{450{1'b0}}, cent_unit_txdprioout[149:0]},
tx_forcedisp_wire = {1'b0},
tx_invpolarity = 1'b0,
tx_localrefclk = {wire_transmit_pma0_clockout},
tx_phfiforeset = 1'b0,
tx_pma_fastrefclk0in = {wire_pll0_clk[0]},
tx_pma_refclk0in = {wire_pll0_clk[1]},
tx_pma_refclk0inpulse = {wire_pll0_clk[2]},
tx_pmadprioin_wire = {{900{1'b0}}, cent_unit_txpmadprioout[299:0]},
tx_pmadprioout = {{900{1'b0}}, wire_transmit_pma0_dprioout},
tx_serialloopbackout = {wire_transmit_pma0_seriallpbkout},
tx_txdprioout = {{450{1'b0}}, wire_transmit_pcs0_dprioout},
txdataout = {wire_transmit_pma0_dataout},
txdetectrxout = {wire_transmit_pcs0_txdetectrx},
w_cent_unit_dpriodisableout1w = {wire_cent_unit0_dpriodisableout};
endmodule //mAltGX_alt_c3gxb
//VALID FILE
 
 
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module mAltGX (
cal_blk_clk,
gxb_powerdown,
pll_inclk,
reconfig_clk,
reconfig_togxb,
rx_analogreset,
rx_datain,
rx_digitalreset,
tx_ctrlenable,
tx_datain,
tx_digitalreset,
pll_locked,
reconfig_fromgxb,
rx_ctrldetect,
rx_dataout,
rx_disperr,
rx_errdetect,
rx_patterndetect,
rx_rlv,
rx_syncstatus,
tx_clkout,
tx_dataout);
 
input cal_blk_clk;
input [0:0] gxb_powerdown;
input [0:0] pll_inclk;
input reconfig_clk;
input [3:0] reconfig_togxb;
input [0:0] rx_analogreset;
input [0:0] rx_datain;
input [0:0] rx_digitalreset;
input [0:0] tx_ctrlenable;
input [7:0] tx_datain;
input [0:0] tx_digitalreset;
output [0:0] pll_locked;
output [4:0] reconfig_fromgxb;
output [0:0] rx_ctrldetect;
output [7:0] rx_dataout;
output [0:0] rx_disperr;
output [0:0] rx_errdetect;
output [0:0] rx_patterndetect;
output [0:0] rx_rlv;
output [0:0] rx_syncstatus;
output [0:0] tx_clkout;
output [0:0] tx_dataout;
 
parameter starting_channel_number = 0;
 
 
wire [0:0] sub_wire0;
wire [0:0] sub_wire1;
wire [4:0] sub_wire2;
wire [0:0] sub_wire3;
wire [0:0] sub_wire4;
wire [0:0] sub_wire5;
wire [7:0] sub_wire6;
wire [0:0] sub_wire7;
wire [0:0] sub_wire8;
wire [0:0] sub_wire9;
wire [0:0] sub_wire10;
wire [0:0] rx_patterndetect = sub_wire0[0:0];
wire [0:0] pll_locked = sub_wire1[0:0];
wire [4:0] reconfig_fromgxb = sub_wire2[4:0];
wire [0:0] rx_disperr = sub_wire3[0:0];
wire [0:0] rx_syncstatus = sub_wire4[0:0];
wire [0:0] rx_ctrldetect = sub_wire5[0:0];
wire [7:0] rx_dataout = sub_wire6[7:0];
wire [0:0] rx_errdetect = sub_wire7[0:0];
wire [0:0] rx_rlv = sub_wire8[0:0];
wire [0:0] tx_clkout = sub_wire9[0:0];
wire [0:0] tx_dataout = sub_wire10[0:0];
 
mAltGX_alt_c3gxb mAltGX_alt_c3gxb_component (
.pll_inclk (pll_inclk),
.reconfig_togxb (reconfig_togxb),
.cal_blk_clk (cal_blk_clk),
.reconfig_clk (reconfig_clk),
.rx_analogreset (rx_analogreset),
.rx_datain (rx_datain),
.rx_digitalreset (rx_digitalreset),
.tx_ctrlenable (tx_ctrlenable),
.tx_datain (tx_datain),
.tx_digitalreset (tx_digitalreset),
.gxb_powerdown (gxb_powerdown),
.rx_patterndetect (sub_wire0),
.pll_locked (sub_wire1),
.reconfig_fromgxb (sub_wire2),
.rx_disperr (sub_wire3),
.rx_syncstatus (sub_wire4),
.rx_ctrldetect (sub_wire5),
.rx_dataout (sub_wire6),
.rx_errdetect (sub_wire7),
.rx_rlv (sub_wire8),
.tx_clkout (sub_wire9),
.tx_dataout (sub_wire10));
defparam
mAltGX_alt_c3gxb_component.starting_channel_number = starting_channel_number;
 
 
endmodule
 
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "1250"
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "1250.0"
// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "125.0"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "GIGE"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "1"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "125.0"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "62.5 125.0"
// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "1250.0"
// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "125.0"
// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "GIGE"
// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "None"
// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
// Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "1250.0 Mbps"
// Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false"
// Retrieval info: CONSTANT: ENABLE_PLL_INCLK_ALT_DRIVE_RX_CRU STRING "true"
// Retrieval info: CONSTANT: ENABLE_PLL_INCLK_DRIVE_RX_CRU STRING "true"
// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
// Retrieval info: CONSTANT: GX_CHANNEL_TYPE STRING ""
// Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "125.0 MHz"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "ANY"
// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
// Retrieval info: CONSTANT: LPM_TYPE STRING "alt_c3gxb"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
// Retrieval info: CONSTANT: PLL_BANDWIDTH_TYPE STRING "Auto"
// Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: PLL_INCLK_PERIOD NUMERIC "8000"
// Retrieval info: CONSTANT: PLL_PFD_FB_MODE STRING "internal"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: PROTOCOL STRING "gige"
// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "0"
// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "8000"
// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "basic"
// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "1250"
// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "8"
// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "10100010010101111100"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "10101011011010000011"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "40"
// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
// Retrieval info: CONSTANT: RX_SIGNAL_DETECT_THRESHOLD NUMERIC "8"
// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "1250"
// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "Auto"
// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "8000"
// Retrieval info: CONSTANT: TX_PLL_TYPE STRING "CMU"
// Retrieval info: CONSTANT: TX_SLEW_RATE STRING "medium"
// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "basic"
// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "4"
// Retrieval info: CONSTANT: equalization_setting NUMERIC "1"
// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
// Retrieval info: CONSTANT: iqtxrxclk_allowed STRING ""
// Retrieval info: CONSTANT: number_of_quads NUMERIC "1"
// Retrieval info: CONSTANT: pll_divide_by STRING "1"
// Retrieval info: CONSTANT: pll_multiply_by STRING "5"
// Retrieval info: CONSTANT: reconfig_calibration STRING "true"
// Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "5"
// Retrieval info: CONSTANT: reconfig_pll_control_width NUMERIC "1"
// Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4"
// Retrieval info: CONSTANT: rx_deskew_pattern STRING "0"
// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "1"
// Retrieval info: CONSTANT: rx_enable_second_order_loop STRING "false"
// Retrieval info: CONSTANT: rx_loop_1_digital_filter NUMERIC "8"
// Retrieval info: CONSTANT: rx_signal_detect_loss_threshold STRING "1"
// Retrieval info: CONSTANT: rx_signal_detect_valid_threshold STRING "14"
// Retrieval info: CONSTANT: rx_use_external_termination STRING "false"
// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
// Retrieval info: CONSTANT: top_module_name STRING "mAltGX"
// Retrieval info: CONSTANT: tx_bitslip_enable STRING "FALSE"
// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "1"
// Retrieval info: CONSTANT: tx_use_external_termination STRING "false"
// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
// Retrieval info: USED_PORT: pll_inclk 0 0 1 0 INPUT NODEFVAL "pll_inclk[0..0]"
// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 5 0 OUTPUT NODEFVAL "reconfig_fromgxb[4..0]"
// Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]"
// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
// Retrieval info: USED_PORT: rx_ctrldetect 0 0 1 0 OUTPUT NODEFVAL "rx_ctrldetect[0..0]"
// Retrieval info: USED_PORT: rx_datain 0 0 1 0 INPUT NODEFVAL "rx_datain[0..0]"
// Retrieval info: USED_PORT: rx_dataout 0 0 8 0 OUTPUT NODEFVAL "rx_dataout[7..0]"
// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
// Retrieval info: USED_PORT: rx_disperr 0 0 1 0 OUTPUT NODEFVAL "rx_disperr[0..0]"
// Retrieval info: USED_PORT: rx_errdetect 0 0 1 0 OUTPUT NODEFVAL "rx_errdetect[0..0]"
// Retrieval info: USED_PORT: rx_patterndetect 0 0 1 0 OUTPUT NODEFVAL "rx_patterndetect[0..0]"
// Retrieval info: USED_PORT: rx_rlv 0 0 1 0 OUTPUT NODEFVAL "rx_rlv[0..0]"
// Retrieval info: USED_PORT: rx_syncstatus 0 0 1 0 OUTPUT NODEFVAL "rx_syncstatus[0..0]"
// Retrieval info: USED_PORT: tx_clkout 0 0 1 0 OUTPUT NODEFVAL "tx_clkout[0..0]"
// Retrieval info: USED_PORT: tx_ctrlenable 0 0 1 0 INPUT NODEFVAL "tx_ctrlenable[0..0]"
// Retrieval info: USED_PORT: tx_datain 0 0 8 0 INPUT NODEFVAL "tx_datain[7..0]"
// Retrieval info: USED_PORT: tx_dataout 0 0 1 0 OUTPUT NODEFVAL "tx_dataout[0..0]"
// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
// Retrieval info: CONNECT: @pll_inclk 0 0 1 0 pll_inclk 0 0 1 0
// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
// Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0
// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
// Retrieval info: CONNECT: @rx_datain 0 0 1 0 rx_datain 0 0 1 0
// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: @tx_ctrlenable 0 0 1 0 tx_ctrlenable 0 0 1 0
// Retrieval info: CONNECT: @tx_datain 0 0 8 0 tx_datain 0 0 8 0
// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
// Retrieval info: CONNECT: reconfig_fromgxb 0 0 5 0 @reconfig_fromgxb 0 0 5 0
// Retrieval info: CONNECT: rx_ctrldetect 0 0 1 0 @rx_ctrldetect 0 0 1 0
// Retrieval info: CONNECT: rx_dataout 0 0 8 0 @rx_dataout 0 0 8 0
// Retrieval info: CONNECT: rx_disperr 0 0 1 0 @rx_disperr 0 0 1 0
// Retrieval info: CONNECT: rx_errdetect 0 0 1 0 @rx_errdetect 0 0 1 0
// Retrieval info: CONNECT: rx_patterndetect 0 0 1 0 @rx_patterndetect 0 0 1 0
// Retrieval info: CONNECT: rx_rlv 0 0 1 0 @rx_rlv 0 0 1 0
// Retrieval info: CONNECT: rx_syncstatus 0 0 1 0 @rx_syncstatus 0 0 1 0
// Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0
// Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL mAltGX.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mAltGX.ppf TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mAltGX.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mAltGX.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mAltGX.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mAltGX_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mAltGX_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: LIB_FILE: cycloneiv_hssi
// Retrieval info: CBX_MODULE_PREFIX: ON
/src/mAltGX/mAltGX.ppf
0,0 → 1,29
<?xml version="1.0" encoding="UTF-8" ?>
<!DOCTYPE pinplan>
<pinplan intended_family="Cyclone IV GX" variation_name="mAltGX" megafunction_name="ALTGX" specifies="all_ports">
<global>
<pin name="cal_blk_clk" direction="input" scope="external" />
<pin name="gxb_powerdown[0..0]" direction="input" scope="external" />
<pin name="pll_inclk[0..0]" direction="input" scope="external" />
<pin name="reconfig_clk" direction="input" scope="external" />
<pin name="reconfig_togxb[3..0]" direction="input" scope="external" />
<pin name="rx_analogreset[0..0]" direction="input" scope="external" />
<pin name="rx_datain[0..0]" direction="input" scope="external" />
<pin name="rx_digitalreset[0..0]" direction="input" scope="external" />
<pin name="tx_ctrlenable[0..0]" direction="input" scope="external" />
<pin name="tx_datain[7..0]" direction="input" scope="external" />
<pin name="tx_digitalreset[0..0]" direction="input" scope="external" />
<pin name="pll_locked[0..0]" direction="output" scope="external" />
<pin name="reconfig_fromgxb[4..0]" direction="output" scope="external" />
<pin name="rx_ctrldetect[0..0]" direction="output" scope="external" />
<pin name="rx_dataout[7..0]" direction="output" scope="external" />
<pin name="rx_disperr[0..0]" direction="output" scope="external" />
<pin name="rx_errdetect[0..0]" direction="output" scope="external" />
<pin name="rx_patterndetect[0..0]" direction="output" scope="external" />
<pin name="rx_rlv[0..0]" direction="output" scope="external" />
<pin name="rx_syncstatus[0..0]" direction="output" scope="external" />
<pin name="tx_clkout[0..0]" direction="output" scope="external" />
<pin name="tx_dataout[0..0]" direction="output" scope="external" />
 
</global>
</pinplan>
/src/mAltGX/mAltGXReconfig.qip
0,0 → 1,3
set_global_assignment -name IP_TOOL_NAME "ALTGX_RECONFIG"
set_global_assignment -name IP_TOOL_VERSION "11.0"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "mAltGXReconfig.v"]
/src/mAltGX/mAltGX.qip
0,0 → 1,4
set_global_assignment -name IP_TOOL_NAME "ALTGX"
set_global_assignment -name IP_TOOL_VERSION "11.0"
set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "mAltGX.v"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "mAltGX.ppf"]
/src/mAltGX/mAltGXReconfig.v
0,0 → 1,529
// megafunction wizard: %ALTGX_RECONFIG%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: alt_c3gxb_reconfig
 
// ============================================================
// File Name: mAltGXReconfig.v
// Megafunction Name(s):
// alt_c3gxb_reconfig
//
// Simulation Library Files(s):
// altera_mf;lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 11.0 Build 157 04/27/2011 SJ Full Version
// ************************************************************
 
 
//Copyright (C) 1991-2011 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
 
 
//alt_c3gxb_reconfig CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone IV GX" ENABLE_BUF_CAL="TRUE" NUMBER_OF_CHANNELS=1 NUMBER_OF_RECONFIG_PORTS=1 RECONFIG_FROMGXB_WIDTH=5 RECONFIG_TOGXB_WIDTH=4 busy reconfig_clk reconfig_fromgxb reconfig_togxb
//VERSION_BEGIN 11.0 cbx_alt_c3gxb_reconfig 2011:04:27:21:07:19:SJ cbx_alt_cal 2011:04:27:21:07:19:SJ cbx_alt_dprio 2011:04:27:21:07:19:SJ cbx_altsyncram 2011:04:27:21:07:19:SJ cbx_cycloneii 2011:04:27:21:07:19:SJ cbx_lpm_add_sub 2011:04:27:21:07:19:SJ cbx_lpm_compare 2011:04:27:21:07:19:SJ cbx_lpm_counter 2011:04:27:21:07:19:SJ cbx_lpm_decode 2011:04:27:21:07:19:SJ cbx_lpm_mux 2011:04:27:21:07:19:SJ cbx_lpm_shiftreg 2011:04:27:21:07:19:SJ cbx_mgl 2011:04:27:21:11:03:SJ cbx_stratix 2011:04:27:21:07:19:SJ cbx_stratixii 2011:04:27:21:07:19:SJ cbx_stratixiii 2011:04:27:21:07:19:SJ cbx_stratixv 2011:04:27:21:07:19:SJ cbx_util_mgl 2011:04:27:21:07:19:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
 
 
 
//alt_dprio address_width=16 CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone IV GX" quad_address_width=9 address busy datain dataout dpclk dpriodisable dprioin dprioload dprioout quad_address rden reset wren wren_data
//VERSION_BEGIN 11.0 cbx_alt_dprio 2011:04:27:21:07:19:SJ cbx_cycloneii 2011:04:27:21:07:19:SJ cbx_lpm_add_sub 2011:04:27:21:07:19:SJ cbx_lpm_compare 2011:04:27:21:07:19:SJ cbx_lpm_counter 2011:04:27:21:07:19:SJ cbx_lpm_decode 2011:04:27:21:07:19:SJ cbx_lpm_shiftreg 2011:04:27:21:07:19:SJ cbx_mgl 2011:04:27:21:11:03:SJ cbx_stratix 2011:04:27:21:07:19:SJ cbx_stratixii 2011:04:27:21:07:19:SJ VERSION_END
 
//synthesis_resources = lpm_compare 3 lpm_counter 1 lpm_decode 1 lut 1 reg 102
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"{-to addr_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to wr_out_data_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to rd_out_data_shift_reg[13]} DPRIO_INTERFACE_REG=ON;{-to in_data_shift_reg[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[1]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[2]} DPRIO_INTERFACE_REG=ON"} *)
module mAltGXReconfig_alt_dprio_v5k
(
address,
busy,
datain,
dataout,
dpclk,
dpriodisable,
dprioin,
dprioload,
dprioout,
quad_address,
rden,
reset,
wren,
wren_data) /* synthesis synthesis_clearbox=2 */;
input [15:0] address;
output busy;
input [15:0] datain;
output [15:0] dataout;
input dpclk;
output dpriodisable;
output dprioin;
output dprioload;
input dprioout;
input [8:0] quad_address;
input rden;
input reset;
input wren;
input wren_data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [15:0] datain;
tri0 rden;
tri0 reset;
tri0 wren;
tri0 wren_data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
 
(* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
reg [31:0] addr_shift_reg;
(* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
reg [15:0] in_data_shift_reg;
(* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
reg [15:0] rd_out_data_shift_reg;
wire [2:0] wire_startup_cntr_d;
(* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
reg [2:0] startup_cntr;
wire [2:0] wire_startup_cntr_ena;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg [2:0] state_mc_reg;
(* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
reg [31:0] wr_out_data_shift_reg;
wire wire_pre_amble_cmpr_aeb;
wire wire_pre_amble_cmpr_agb;
wire wire_rd_data_output_cmpr_ageb;
wire wire_rd_data_output_cmpr_alb;
wire wire_state_mc_cmpr_aeb;
wire [5:0] wire_state_mc_counter_q;
wire [7:0] wire_state_mc_decode_eq;
wire wire_dprioin_mux_dataout;
wire busy_state;
wire idle_state;
wire rd_addr_done;
wire rd_addr_state;
wire rd_data_done;
wire rd_data_input_state;
wire rd_data_output_state;
wire rd_data_state;
wire rdinc;
wire read_state;
wire s0_to_0;
wire s0_to_1;
wire s1_to_0;
wire s1_to_1;
wire s2_to_0;
wire s2_to_1;
wire startup_done;
wire startup_idle;
wire wr_addr_done;
wire wr_addr_state;
wire wr_data_done;
wire wr_data_state;
wire write_state;
 
// synopsys translate_off
initial
addr_shift_reg = 0;
// synopsys translate_on
always @ ( posedge dpclk or posedge reset)
if (reset == 1'b1) addr_shift_reg <= 32'b0;
else
if (wire_pre_amble_cmpr_aeb == 1'b1) addr_shift_reg <= {{2{{2{1'b0}}}}, 1'b0, quad_address[8:0], 2'b10, address};
else addr_shift_reg <= {addr_shift_reg[30:0], 1'b0};
// synopsys translate_off
initial
in_data_shift_reg = 0;
// synopsys translate_on
always @ ( posedge dpclk or posedge reset)
if (reset == 1'b1) in_data_shift_reg <= 16'b0;
else if (rd_data_input_state == 1'b1) in_data_shift_reg <= {in_data_shift_reg[14:0], dprioout};
// synopsys translate_off
initial
rd_out_data_shift_reg = 0;
// synopsys translate_on
always @ ( posedge dpclk or posedge reset)
if (reset == 1'b1) rd_out_data_shift_reg <= 16'b0;
else
if (wire_pre_amble_cmpr_aeb == 1'b1) rd_out_data_shift_reg <= {{2{1'b0}}, {2{1'b1}}, 1'b0, quad_address, 2'b10};
else rd_out_data_shift_reg <= {rd_out_data_shift_reg[14:0], 1'b0};
// synopsys translate_off
initial
startup_cntr[0:0] = 0;
// synopsys translate_on
always @ ( posedge dpclk)
if (wire_startup_cntr_ena[0:0] == 1'b1)
if (reset == 1'b1) startup_cntr[0:0] <= 1'b0;
else startup_cntr[0:0] <= wire_startup_cntr_d[0:0];
// synopsys translate_off
initial
startup_cntr[1:1] = 0;
// synopsys translate_on
always @ ( posedge dpclk)
if (wire_startup_cntr_ena[1:1] == 1'b1)
if (reset == 1'b1) startup_cntr[1:1] <= 1'b0;
else startup_cntr[1:1] <= wire_startup_cntr_d[1:1];
// synopsys translate_off
initial
startup_cntr[2:2] = 0;
// synopsys translate_on
always @ ( posedge dpclk)
if (wire_startup_cntr_ena[2:2] == 1'b1)
if (reset == 1'b1) startup_cntr[2:2] <= 1'b0;
else startup_cntr[2:2] <= wire_startup_cntr_d[2:2];
assign
wire_startup_cntr_d = {(startup_cntr[2] ^ (startup_cntr[1] & startup_cntr[0])), (startup_cntr[0] ^ startup_cntr[1]), (~ startup_cntr[0])};
assign
wire_startup_cntr_ena = {3{((((rden | wren) | rdinc) | (~ startup_idle)) & (~ startup_done))}};
// synopsys translate_off
initial
state_mc_reg = 0;
// synopsys translate_on
always @ ( posedge dpclk or posedge reset)
if (reset == 1'b1) state_mc_reg <= 3'b0;
else state_mc_reg <= {(s2_to_1 | (((~ s2_to_0) & (~ s2_to_1)) & state_mc_reg[2])), (s1_to_1 | (((~ s1_to_0) & (~ s1_to_1)) & state_mc_reg[1])), (s0_to_1 | (((~ s0_to_0) & (~ s0_to_1)) & state_mc_reg[0]))};
// synopsys translate_off
initial
wr_out_data_shift_reg = 0;
// synopsys translate_on
always @ ( posedge dpclk or posedge reset)
if (reset == 1'b1) wr_out_data_shift_reg <= 32'b0;
else
if (wire_pre_amble_cmpr_aeb == 1'b1) wr_out_data_shift_reg <= {{2{1'b0}}, 2'b01, 1'b0, quad_address[8:0], 2'b10, datain};
else wr_out_data_shift_reg <= {wr_out_data_shift_reg[30:0], 1'b0};
lpm_compare pre_amble_cmpr
(
.aeb(wire_pre_amble_cmpr_aeb),
.agb(wire_pre_amble_cmpr_agb),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.dataa(wire_state_mc_counter_q),
.datab(6'b011111)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pre_amble_cmpr.lpm_width = 6,
pre_amble_cmpr.lpm_type = "lpm_compare";
lpm_compare rd_data_output_cmpr
(
.aeb(),
.agb(),
.ageb(wire_rd_data_output_cmpr_ageb),
.alb(wire_rd_data_output_cmpr_alb),
.aleb(),
.aneb(),
.dataa(wire_state_mc_counter_q),
.datab(6'b110000)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
rd_data_output_cmpr.lpm_width = 6,
rd_data_output_cmpr.lpm_type = "lpm_compare";
lpm_compare state_mc_cmpr
(
.aeb(wire_state_mc_cmpr_aeb),
.agb(),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.dataa(wire_state_mc_counter_q),
.datab({6{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
state_mc_cmpr.lpm_width = 6,
state_mc_cmpr.lpm_type = "lpm_compare";
lpm_counter state_mc_counter
(
.clock(dpclk),
.cnt_en((write_state | read_state)),
.cout(),
.eq(),
.q(wire_state_mc_counter_q),
.sclr(reset)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.aset(1'b0),
.cin(1'b1),
.clk_en(1'b1),
.data({6{1'b0}}),
.sload(1'b0),
.sset(1'b0),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
state_mc_counter.lpm_port_updown = "PORT_UNUSED",
state_mc_counter.lpm_width = 6,
state_mc_counter.lpm_type = "lpm_counter";
lpm_decode state_mc_decode
(
.data(state_mc_reg),
.eq(wire_state_mc_decode_eq)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0),
.enable(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
state_mc_decode.lpm_decodes = 8,
state_mc_decode.lpm_width = 3,
state_mc_decode.lpm_type = "lpm_decode";
or(wire_dprioin_mux_dataout, ((((((wr_addr_state | rd_addr_state) & addr_shift_reg[31]) & wire_pre_amble_cmpr_agb) | ((~ wire_pre_amble_cmpr_agb) & (wr_addr_state | rd_addr_state))) | (((wr_data_state & wr_out_data_shift_reg[31]) & wire_pre_amble_cmpr_agb) | ((~ wire_pre_amble_cmpr_agb) & wr_data_state))) | (((rd_data_output_state & rd_out_data_shift_reg[15]) & wire_pre_amble_cmpr_agb) | ((~ wire_pre_amble_cmpr_agb) & rd_data_output_state))), ~(((write_state | rd_addr_state) | rd_data_output_state)));
assign
busy = busy_state,
busy_state = (write_state | read_state),
dataout = in_data_shift_reg,
dpriodisable = (~ (startup_cntr[2] & (startup_cntr[0] | startup_cntr[1]))),
dprioin = wire_dprioin_mux_dataout,
dprioload = (~ ((startup_cntr[0] ^ startup_cntr[1]) & (~ startup_cntr[2]))),
idle_state = wire_state_mc_decode_eq[0],
rd_addr_done = (rd_addr_state & wire_state_mc_cmpr_aeb),
rd_addr_state = (wire_state_mc_decode_eq[5] & startup_done),
rd_data_done = (rd_data_state & wire_state_mc_cmpr_aeb),
rd_data_input_state = (wire_rd_data_output_cmpr_ageb & rd_data_state),
rd_data_output_state = (wire_rd_data_output_cmpr_alb & rd_data_state),
rd_data_state = (wire_state_mc_decode_eq[7] & startup_done),
rdinc = 1'b0,
read_state = (rd_addr_state | rd_data_state),
s0_to_0 = ((wr_data_state & wr_data_done) | (rd_data_state & rd_data_done)),
s0_to_1 = (((idle_state & (wren | ((~ wren) & ((rden | rdinc) | wren_data)))) | (wr_addr_state & wr_addr_done)) | (rd_addr_state & rd_addr_done)),
s1_to_0 = (((wr_data_state & wr_data_done) | (rd_data_state & rd_data_done)) | (idle_state & (wren | (((~ wren) & (~ wren_data)) & rden)))),
s1_to_1 = (((idle_state & ((~ wren) & (rdinc | wren_data))) | (wr_addr_state & wr_addr_done)) | (rd_addr_state & rd_addr_done)),
s2_to_0 = ((((wr_addr_state & wr_addr_done) | (wr_data_state & wr_data_done)) | (rd_data_state & rd_data_done)) | (idle_state & (wren | wren_data))),
s2_to_1 = ((idle_state & (((~ wren) & (~ wren_data)) & (rdinc | rden))) | (rd_addr_state & rd_addr_done)),
startup_done = ((startup_cntr[2] & (~ startup_cntr[0])) & startup_cntr[1]),
startup_idle = ((~ startup_cntr[0]) & (~ (startup_cntr[2] ^ startup_cntr[1]))),
wr_addr_done = (wr_addr_state & wire_state_mc_cmpr_aeb),
wr_addr_state = (wire_state_mc_decode_eq[1] & startup_done),
wr_data_done = (wr_data_state & wire_state_mc_cmpr_aeb),
wr_data_state = (wire_state_mc_decode_eq[3] & startup_done),
write_state = (wr_addr_state | wr_data_state);
endmodule //mAltGXReconfig_alt_dprio_v5k
 
//synthesis_resources = alt_cal_c3gxb 1 lpm_compare 3 lpm_counter 1 lpm_decode 1 lut 1 reg 114
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"{-to address_pres_reg[11]} DPRIO_CHANNEL_NUM=11;{-to address_pres_reg[10]} DPRIO_CHANNEL_NUM=10;{-to address_pres_reg[9]} DPRIO_CHANNEL_NUM=9;{-to address_pres_reg[8]} DPRIO_CHANNEL_NUM=8;{-to address_pres_reg[7]} DPRIO_CHANNEL_NUM=7;{-to address_pres_reg[6]} DPRIO_CHANNEL_NUM=6;{-to address_pres_reg[5]} DPRIO_CHANNEL_NUM=5;{-to address_pres_reg[4]} DPRIO_CHANNEL_NUM=4;{-to address_pres_reg[3]} DPRIO_CHANNEL_NUM=3;{-to address_pres_reg[2]} DPRIO_CHANNEL_NUM=2;{-to address_pres_reg[1]} DPRIO_CHANNEL_NUM=1;{-to address_pres_reg[0]} DPRIO_CHANNEL_NUM=0"} *)
module mAltGXReconfig_alt_c3gxb_reconfig_nrm
(
busy,
reconfig_clk,
reconfig_fromgxb,
reconfig_togxb) /* synthesis synthesis_clearbox=2 */;
output busy;
input reconfig_clk;
input [4:0] reconfig_fromgxb;
output [3:0] reconfig_togxb;
 
wire wire_calibration_c3gxb_busy;
wire [15:0] wire_calibration_c3gxb_dprio_addr;
wire [15:0] wire_calibration_c3gxb_dprio_dataout;
wire wire_calibration_c3gxb_dprio_rden;
wire wire_calibration_c3gxb_dprio_wren;
wire [8:0] wire_calibration_c3gxb_quad_addr;
wire wire_calibration_c3gxb_retain_addr;
wire wire_dprio_busy;
wire [15:0] wire_dprio_dataout;
wire wire_dprio_dpriodisable;
wire wire_dprio_dprioin;
wire wire_dprio_dprioload;
(* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON"} *)
reg [11:0] address_pres_reg;
wire cal_busy;
wire [0:0] cal_dprioout_wire;
wire [0:0] cal_testbuses;
wire [2:0] channel_address;
wire [15:0] dprio_address;
wire offset_cancellation_reset;
wire [8:0] quad_address;
wire reconfig_reset_all;
 
alt_cal_c3gxb calibration_c3gxb
(
.busy(wire_calibration_c3gxb_busy),
.cal_error(),
.clock(reconfig_clk),
.dprio_addr(wire_calibration_c3gxb_dprio_addr),
.dprio_busy(wire_dprio_busy),
.dprio_datain(wire_dprio_dataout),
.dprio_dataout(wire_calibration_c3gxb_dprio_dataout),
.dprio_rden(wire_calibration_c3gxb_dprio_rden),
.dprio_wren(wire_calibration_c3gxb_dprio_wren),
.quad_addr(wire_calibration_c3gxb_quad_addr),
.remap_addr(address_pres_reg),
.reset((offset_cancellation_reset | reconfig_reset_all)),
.retain_addr(wire_calibration_c3gxb_retain_addr),
.testbuses(cal_testbuses)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.start(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
calibration_c3gxb.channel_address_width = 0,
calibration_c3gxb.number_of_channels = 1,
calibration_c3gxb.sim_model_mode = "FALSE",
calibration_c3gxb.lpm_type = "alt_cal_c3gxb";
mAltGXReconfig_alt_dprio_v5k dprio
(
.address(({16{wire_calibration_c3gxb_busy}} & dprio_address)),
.busy(wire_dprio_busy),
.datain(({16{wire_calibration_c3gxb_busy}} & wire_calibration_c3gxb_dprio_dataout)),
.dataout(wire_dprio_dataout),
.dpclk(reconfig_clk),
.dpriodisable(wire_dprio_dpriodisable),
.dprioin(wire_dprio_dprioin),
.dprioload(wire_dprio_dprioload),
.dprioout(cal_dprioout_wire),
.quad_address(address_pres_reg[11:3]),
.rden((wire_calibration_c3gxb_busy & wire_calibration_c3gxb_dprio_rden)),
.reset(reconfig_reset_all),
.wren((wire_calibration_c3gxb_busy & wire_calibration_c3gxb_dprio_wren)),
.wren_data(wire_calibration_c3gxb_retain_addr));
// synopsys translate_off
initial
address_pres_reg = 0;
// synopsys translate_on
always @ ( posedge reconfig_clk or posedge reconfig_reset_all)
if (reconfig_reset_all == 1'b1) address_pres_reg <= 12'b0;
else address_pres_reg <= {quad_address, channel_address};
assign
busy = cal_busy,
cal_busy = wire_calibration_c3gxb_busy,
cal_dprioout_wire = {reconfig_fromgxb[0]},
cal_testbuses = {reconfig_fromgxb[1]},
channel_address = wire_calibration_c3gxb_dprio_addr[14:12],
dprio_address = {wire_calibration_c3gxb_dprio_addr[15], address_pres_reg[2:0], wire_calibration_c3gxb_dprio_addr[11:0]},
offset_cancellation_reset = 1'b0,
quad_address = wire_calibration_c3gxb_quad_addr,
reconfig_reset_all = 1'b0,
reconfig_togxb = {wire_calibration_c3gxb_busy, wire_dprio_dprioload, wire_dprio_dpriodisable, wire_dprio_dprioin};
endmodule //mAltGXReconfig_alt_c3gxb_reconfig_nrm
//VALID FILE
 
 
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module mAltGXReconfig (
reconfig_clk,
reconfig_fromgxb,
busy,
reconfig_togxb)/* synthesis synthesis_clearbox = 2 */;
 
input reconfig_clk;
input [4:0] reconfig_fromgxb;
output busy;
output [3:0] reconfig_togxb;
 
wire sub_wire0;
wire [3:0] sub_wire1;
wire busy = sub_wire0;
wire [3:0] reconfig_togxb = sub_wire1[3:0];
 
mAltGXReconfig_alt_c3gxb_reconfig_nrm mAltGXReconfig_alt_c3gxb_reconfig_nrm_component (
.reconfig_clk (reconfig_clk),
.reconfig_fromgxb (reconfig_fromgxb),
.busy (sub_wire0),
.reconfig_togxb (sub_wire1))/* synthesis synthesis_clearbox=2
clearbox_macroname = alt_c3gxb_reconfig
clearbox_defparam = "cbx_blackbox_list=-lpm_mux;intended_device_family=Cyclone IV GX;number_of_channels=1;number_of_reconfig_ports=1;enable_buf_cal=true;reconfig_fromgxb_width=5;reconfig_togxb_width=4;" */;
 
endmodule
 
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADCE NUMERIC "0"
// Retrieval info: PRIVATE: CMU_PLL NUMERIC "0"
// Retrieval info: PRIVATE: DATA_RATE NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: PRIVATE: PMA NUMERIC "0"
// Retrieval info: PRIVATE: PROTO_SWITCH NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: CONSTANT: CBX_BLACKBOX_LIST STRING "-lpm_mux"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
// Retrieval info: CONSTANT: NUMBER_OF_RECONFIG_PORTS NUMERIC "1"
// Retrieval info: CONSTANT: enable_buf_cal STRING "true"
// Retrieval info: CONSTANT: reconfig_fromgxb_width NUMERIC "5"
// Retrieval info: CONSTANT: reconfig_togxb_width NUMERIC "4"
// Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 5 0 INPUT NODEFVAL "reconfig_fromgxb[4..0]"
// Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 OUTPUT NODEFVAL "reconfig_togxb[3..0]"
// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
// Retrieval info: CONNECT: @reconfig_fromgxb 0 0 5 0 reconfig_fromgxb 0 0 5 0
// Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
// Retrieval info: CONNECT: reconfig_togxb 0 0 4 0 @reconfig_togxb 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL mAltGXReconfig.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL mAltGXReconfig.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mAltGXReconfig.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mAltGXReconfig.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mAltGXReconfig_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL mAltGXReconfig_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: LIB_FILE: lpm
/src/mAltGX
src/mAltGX Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property Index: src/mRateAdapter.v =================================================================== --- src/mRateAdapter.v (nonexistent) +++ src/mRateAdapter.v (revision 2) @@ -0,0 +1,123 @@ +/* +Developed By Subtleware Corporation Pte Ltd 2011 +File : +Description : +Remarks : +Revision : + Date Author Description +02/09/12 Jefflieu +*/ +module mRateAdapter( + //MAC Side signal + input i_TxClk, + input i_TxEN, + input i_TxER, + input [07:00] i8_TxD, + + input i_RxClk, + output o_RxEN, + output o_RxER, + output [07:00] o8_RxD, + + input [1:0] i2_Speed, + + //SGMII PHY side + input i_SamplingClk, + input i_GClk, + output o_TxEN, + output o_TxER, + output [07:00] o8_TxD, + + input i_RxEN, + input i_RxER, + input [07:00] i8_RxD +); + + wire w_TxActive; + reg r_TxActive; + reg r_GTxEN; + reg r_GTxER; + reg [07:00] r8_GByte; + reg [07:00] r8_Byte; + reg [03:00] r4_LowNib; + reg r_HighNib; + reg r_TxEN_D; + reg r_TxER_D; + reg r_Active; + wire w_TxSop; + wire w_TxEop; + + assign w_TxActive = i_TxEN & i_TxER; + assign w_TxSop = (~r_TxActive && w_TxActive); + assign w_TxEop = (r_TxActive && ~w_TxActive); + + always@(posedge i_TxClk) + begin + r_TxActive <= w_TxActive; + + r_HighNib <= (w_TxSop)?1'b1:(~r_HighNib); + + if(w_TxActive) begin + if(r_HighNib) r8_Byte <= {i8_TxD[3:0],r4_LowNib}; + if(r_HighNib && (~w_TxSop)) r_TxEN_D <= i_TxEN; + if(r_HighNib && (~w_TxSop)) r_TxER_D <= i_TxER; + end else + begin + r_TxEN_D <= 1'b0; + r_TxER_D <= 1'b0; + end + if((~r_HighNib)|| (w_TxSop)) + r4_LowNib <= i8_TxD[3:0]; + + end + + always@(posedge i_GClk) + begin + if(i_SamplingClk==1'b1) begin + r8_GByte <= r8_Byte; + r_GTxEN <= r_TxEN_D; + r_GTxER <= r_TxER_D; + end + end + + assign o8_TxD = (i2_Speed==2'b10)?i8_TxD:r8_GByte; + assign o_TxEN = (i2_Speed==2'b10)?i_TxEN:r_GTxEN; + assign o_TxER = (i2_Speed==2'b10)?i_TxER:r_GTxER; + + + //Receive + //Receive Counter + wire w_RxActive; + reg r_RxActive; + reg [03:00] r4_Cntr; + wire w_RxSop; + wire w_RxEop; + reg [05:00] r6_GByte; + reg [05:00] r6_MByte; + + assign w_RxSop = (~r_RxActive & w_RxActive); + + assign w_RxActive = i_RxEN | i_RxER; + + always@(posedge i_GClk) + begin + r_RxActive <= w_RxActive; + if(w_RxSop) r4_Cntr<=4'h0; + else if(w_RxActive) r4_Cntr <= ((r4_Cntr==4'h9)?4'h0:(r4_Cntr+4'h1)); + if(r4_Cntr==4'h0) r6_GByte <= {i_RxEN,i_RxER,i8_RxD[3:0]}; + else if(r4_Cntr==4'h5) r6_GByte <= {i_RxEN,i_RxER,i8_RxD[7:4]}; + end + + always@(posedge i_RxClk) + begin + r6_MByte <= r6_GByte; + end + + + assign o8_RxD = (i2_Speed==2'b10)?i8_RxD:{r6_MByte[3:0],r6_MByte[3:0]}; + assign o_RxEN = (i2_Speed==2'b10)?i_RxEN:r6_MByte[5]; + assign o_RxER = (i2_Speed==2'b10)?i_RxER:r6_MByte[4]; + + + +endmodule Index: src/SGMIIDefs.v =================================================================== --- src/SGMIIDefs.v (nonexistent) +++ src/SGMIIDefs.v (revision 2) @@ -0,0 +1,21 @@ +`define cSystemClkPeriod 8 + +`define cXmitCONFIG 3'b010 +`define cXmitIDLE 3'b001 +`define cXmitDATA 3'b100 + +`define D0_0 8'h00 +`define D21_5 8'hB5 +`define D2_2 8'h42 +`define D5_6 8'hC5 +`define D16_2 8'h50 +`define K28_5 8'hBC +`define K23_7 8'hF7 //R/ +`define K27_7 8'hFB //S/ +`define K29_7 8'hFD //T/ +`define K30_7 8'hFE //V/ + +`define cReg4Default 16'h0000 +`define cReg0Default 16'h0000 +`define cRegXDefault 16'h0000 +`define cRegLinkTimerDefault (10_000_000/8) \ No newline at end of file Index: src =================================================================== --- src (nonexistent) +++ src (revision 2)
src Property changes : Added: bugtraq:number ## -0,0 +1 ## +true \ No newline at end of property

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