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URL https://opencores.org/ocsvn/sgmii/sgmii/trunk

Subversion Repositories sgmii

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  • This comparison shows the changes necessary to convert path 
    /sgmii/trunk
    from Rev 14 to Rev 15
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Rev 14 → Rev 15

/src/mSyncCtrl.v
1,5 → 1,20
/*
Developed By Subtleware Corporation Pte Ltd 2011
Copyright � 2012 JeffLieu-lieumychuong@gmail.com
 
This file is part of SGMII-IP-Core.
SGMII-IP-Core is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
 
SGMII-IP-Core is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with SGMII-IP-Core. If not, see <http://www.gnu.org/licenses/>.
 
File :
Description :
Remarks :
45,7 → 60,7
localparam stSYNC_ACQUIRED_1 = 13'h0040;
localparam stSYNC_ACQUIRED_2 = 13'h0080;
localparam stSYNC_ACQUIRED_2A = 13'h0100;
localparam stSYNC_ACQUIRED_3 = 13'h0100;
localparam stSYNC_ACQUIRED_3 = 13'h0200;
localparam stSYNC_ACQUIRED_3A = 13'h0400;
localparam stSYNC_ACQUIRED_4 = 13'h0800;
localparam stSYNC_ACQUIRED_4A = 13'h1000;
/src/mTransmit.v
55,13 → 55,13
localparam stEPD2_NOEXT= 24'h040000; //Second Cycle of EPD, transmitting /R/
localparam stEPD3 = 24'h080000; //Third Cycle of EPD, transmitting /R/
localparam stCARR_EXT = 24'h100000; //Carrier extension
localparam stALIGN_ERR = 24'h200000; //Repeater's state, we don't use this, go straight to START ERR
localparam stSTART_ERR = 24'h400000; //Repeater's state
localparam stTX_ERR = 24'h800000; //Repeater's state
//localparam stALIGN_ERR = 24'h200000; //Repeater's state, we don't use this, go straight to START ERR
localparam stSTART_ERR = 24'h200000; //Repeater's state
localparam stTX_ERR = 24'h400000; //Repeater's state
 
reg [23:00] r24_State;
reg [23:00] w24_NxtState;
reg [22:00] r13_State;
reg [22:00] w24_NxtState;
wire w_XmitChange;
75,7 → 75,7
wire [07:00] w8_FifoData;
wire w_UpdateXmitChange;
wire w_ResetState;
wire r_ToTxData; //This signal used in txIDLE_DATA state to comeback to TXIDLE or TXDATA
reg r_ToTxData; //This signal used in txIDLE_DATA state to comeback to TXIDLE or TXDATA
wire w_Disparity;
wire [09:00] w10_FifoDin;
wire [09:00] w10_FifoQ;
83,9 → 83,9
reg [07:00] r8_TxData;
assign w_XmitChange = (r3_LstXmit!=i3_Xmit)?1'b1:1'b0;
assign w_TxOSIndicate = (r24_State==stCONFIG_C1A||r24_State==stCONFIG_C1B||r24_State==stCONFIG_C1C||
r24_State==stCONFIG_C2A||r24_State==stCONFIG_C2B||r24_State==stCONFIG_C2C||
r24_State==stTX_IDLE||r24_State==stTX_DATA)?1'b0:1'b1;
assign w_TxOSIndicate = (r13_State==stCONFIG_C1A||r13_State==stCONFIG_C1B||r13_State==stCONFIG_C1C||
r13_State==stCONFIG_C2A||r13_State==stCONFIG_C2B||r13_State==stCONFIG_C2C||
r13_State==stTX_IDLE||r13_State==stTX_DATA)?1'b0:1'b1;
//assign w_UpdateXmitChange =
//FIFO
assign w10_FifoDin = {i_TxEN,i_TxER,i8_TxD};
102,32 → 102,43
.i_Clk(i_Clk),
.i_ARst_L(i_ARst_L));
//END FIFO
assign w_FifoRd = ((w_FifoTxEn && (r24_State==stXMIT_DATA||r24_State==stTX_IDLE)))?1'b0:1'b1;
assign w_FifoRd = ((w_FifoTxEn && (r13_State==stXMIT_DATA||r13_State==stTX_IDLE)))?1'b0:1'b1;
always@(posedge i_Clk or negedge i_ARst_L)
if(i_ARst_L==1'b0) begin
r24_State <= stTX_TEST;
r3_LstXmit <= 3'b000;
r13_State <= stTX_TEST;
r3_LstXmit <= `cXmitIDLE;
r_TxEven <= 1'b0;
o_TxEven <= 1'b1;
end
else
begin
if(w_UpdateXmitChange) r3_LstXmit <= i3_Xmit;
r24_State <= w24_NxtState;
if(w_ResetState)
r13_State <= stTX_TEST;
else
r13_State <= w24_NxtState;
r_TxEven <= ~r_TxEven;
o_TxEven <= r_TxEven;
end
// always@(posedge i_Clk or posedge w_ResetState)
// if(w_ResetState)
// r13_State <= stTX_TEST;
// else
// r13_State <= w24_NxtState;
assign w_UpdateXmitChange = w_ResetState;
assign w_ResetState = (i_ARst_L==1'b0)||(w_XmitChange && (r_TxEven==1'b0) && w_TxOSIndicate);
assign w_ResetState = (i_ARst_L==1'b0)||(w_XmitChange && (o_TxEven==1'b0) && w_TxOSIndicate);
assign w_Disparity = i_CurrentParity;
always@(*)
begin
if(w_ResetState)
r24_State <= stTX_TEST;
case(r24_State)
stTX_TEST : if(i3_Xmit==`cXmitCONFIG && r_TxEven==1'b0) w24_NxtState <= stCONFIG_C1A; else
if(i3_Xmit==`cXmitIDLE || (i3_Xmit==`cXmitDATA && (w_FifoTxEn || w_FifoTxEr))) w24_NxtState <= stTX_IDLE; else
// else
case(r13_State)
stTX_TEST : if(i3_Xmit==`cXmitCONFIG && o_TxEven==1'b0) w24_NxtState <= stCONFIG_C1A; else
if((i3_Xmit==`cXmitIDLE &&(~o_TxEven)) || ((~o_TxEven) && i3_Xmit==`cXmitDATA && (w_FifoTxEn || w_FifoTxEr))) w24_NxtState <= stTX_IDLE; else
if(i3_Xmit==`cXmitDATA && (~w_FifoTxEn) && (~w_FifoTxEr)) w24_NxtState <= stXMIT_DATA;
else w24_NxtState <= stTX_TEST;
stCONFIG_C1A : w24_NxtState <= stCONFIG_C1B;
219,14 → 230,16
stTX_IDLE : begin
o8_TxCodeGroupOut <= `K28_5;
o_TxCodeCtrl <= 1'b1;
r_ToTxData <= 1'b0;
end
stIDLE_DATA : begin
o8_TxCodeGroupOut <= (w_Disparity==1'b0)?`D5_6:`D16_2;//Disparity = 0 means positive
o8_TxCodeGroupOut <= (w_Disparity==1'b1)?`D5_6:`D16_2;//Disparity = 1 means positive
o_TxCodeCtrl <= 1'b0;
end
stXMIT_DATA : begin
o8_TxCodeGroupOut <= `K28_5;
o_TxCodeCtrl <= 1'b1;
r_ToTxData <= 1'b1;
end
stTX_DATA : if(((~w_FifoTxEn) & w_FifoTxEr & w8_FifoData != 8'h0F)||(w_FifoTxEn & w_FifoTxEr))
begin
304,7 → 317,7
//synthesis translate_off
reg [239:0] r240_TxStateName;
always@(*)
case(r24_State)
case(r13_State)
stTX_TEST : r240_TxStateName<="stTX_TEST ";
stCONFIG_C1A : r240_TxStateName<="stCONFIG_C1A";
stCONFIG_C1B : r240_TxStateName<="stCONFIG_C1B";
326,7 → 339,7
stEPD2_NOEXT : r240_TxStateName<="stEPD2_NOEXT";
stEPD3 : r240_TxStateName<="stEPD3 ";
stCARR_EXT : r240_TxStateName<="stCARR_EXT ";
stALIGN_ERR : r240_TxStateName<="stALIGN_ERR";
//stALIGN_ERR : r240_TxStateName<="stALIGN_ERR";
stSTART_ERR : r240_TxStateName<="stSTART_ERR";
stTX_ERR : r240_TxStateName<="stTX_ERR ";
endcase
/src/mReceive.v
61,23 → 61,22
stRX_CD = 21'h000010,
stRX_INVALID = 21'h000020,
stIDLE_D = 21'h000040,
stCARRIER_DTEC = 21'h000080,
stFALSE_CARRIER = 21'h000100,
stSTART_OF_PKT = 21'h000200,
stRECEIVE = 21'h000400,
stEARLY_END = 21'h000800,
stTRI_RRI = 21'h001000,
stTRR_EXTEND = 21'h002000,
stEPD2_CHK_END = 21'h004000,
stPKT_BURST_RRS = 21'h008000,
stRX_DATA_ERR = 21'h010000,
stRX_DATA = 21'h020000,
stEARLY_END_EXT = 21'h040000,
stEXT_ERROR = 21'h080000,
stLINK_FAILED = 21'h100000;
stFALSE_CARRIER = 21'h000080,
stSTART_OF_PKT = 21'h000100,
stEARLY_END = 21'h000200,
stTRI_RRI = 21'h000400,
stTRR_EXTEND = 21'h000800,
stPKT_BURST_RRS = 21'h001000,
stRX_DATA_ERR = 21'h002000,
stRX_DATA = 21'h004000,
stEARLY_END_EXT = 21'h008000,
stEXT_ERROR = 21'h010000;
reg [20:00] r21_State;
reg [20:00] r21_NxtState;
reg [16:00] r17_State;
reg [16:00] r21_NxtState;
 
wire wSUDIK28_5;
wire wSUDID21_5;
98,7 → 97,7
reg [8*30-1:0] rvStateName;
always@(*)
begin
case(r21_State)
case(r17_State)
stWAIT_FOR_K : rvStateName <= "Wait For K";
stRX_K : rvStateName <= "RX K";
stRX_CB : rvStateName <= "RX CB";
106,20 → 105,20
stRX_CD : rvStateName <= "RX CD";
stRX_INVALID : rvStateName <= "RX Invalid";
stIDLE_D : rvStateName <= "IDLE D";
stCARRIER_DTEC : rvStateName <= "CARRIER DETECT";
//stCARRIER_DTEC : rvStateName <= "CARRIER DETECT";
stFALSE_CARRIER : rvStateName <= "FALSE CARRIER";
stSTART_OF_PKT : rvStateName <= "Start of Packet";
stRECEIVE : rvStateName <= "Receiving";
//stRECEIVE : rvStateName <= "Receiving";
stEARLY_END : rvStateName <= "Early End";
stTRI_RRI : rvStateName <= "TRI RRI";
stTRR_EXTEND : rvStateName <= "TRR Extend";
stEPD2_CHK_END : rvStateName <= "EPD2 Check End";
//stEPD2_CHK_END : rvStateName <= "EPD2 Check End";
stPKT_BURST_RRS : rvStateName <= "PKT BURST RRS";
stRX_DATA_ERR : rvStateName <= "RX DATA Error";
stRX_DATA : rvStateName <= "RX DATA";
stEARLY_END_EXT : rvStateName <= "Early End Ext";
stEXT_ERROR : rvStateName <= "Ext Error";
stLINK_FAILED : rvStateName <= "Link Failed";
//stLINK_FAILED : rvStateName <= "Link Failed";
endcase
//$display("mReceive State: %s",rvStateName);
end
132,9 → 131,9
always@(posedge i_Clk or negedge i_ARst_L)
if(i_ARst_L==1'b0) begin
r21_State <= stWAIT_FOR_K;
r17_State <= stWAIT_FOR_K;
end else begin
r21_State <= r21_NxtState;
r17_State <= r21_NxtState;
end
assign wSUDIK28_5 = (!i_RxCodeInvalid) && (i_RxCodeCtrl) && (i8_RxCodeGroupIn==`K28_5);
142,7 → 141,7
assign wSUDID2_2 = (!i_RxCodeInvalid) && (!i_RxCodeCtrl) && (i8_RxCodeGroupIn==`D2_2);
always@(*)
begin
case(r21_State)
case(r17_State)
stWAIT_FOR_K: if(i_IsComma && i_RxEven) r21_NxtState <= stRX_K; else r21_NxtState<=stWAIT_FOR_K;
stRX_K : if(wSUDID21_5||wSUDID2_2)
r21_NxtState <= stRX_CB; else
240,9 → 239,9
endcase
end
 
assign o_RUDIConfig = (r21_State==stRX_CD )?1'b1:1'b0;
assign o_RUDIIdle = (r21_State==stIDLE_D )?1'b1:1'b0;
assign o_RUDIInvalid= (r21_State==stRX_INVALID && i3_Xmit==`cXmitCONFIG)?1'b1:1'b0;
assign o_RUDIConfig = (r17_State==stRX_CD )?1'b1:1'b0;
assign o_RUDIIdle = (r17_State==stIDLE_D )?1'b1:1'b0;
assign o_RUDIInvalid= (r17_State==stRX_INVALID && i3_Xmit==`cXmitCONFIG)?1'b1:1'b0;
 
always@(posedge i_Clk or negedge i_ARst_L)
if(i_ARst_L==1'b0) begin
308,18 → 307,18
o_RxDV <= 1'b0;
o8_RxD <= 8'b0001_1111;
end
stLINK_FAILED : begin
if(o_Receiving==1'b1)
begin
o_Receiving <= 1'b0;
o_RxER <= 1'b1;
end else
begin
o_RxDV <= 1'b0;
o_RxER <= 1'b0;
end
if(i3_Xmit!=`cXmitDATA) o_Invalid <= 1'b1;
end
// stLINK_FAILED : begin
// if(o_Receiving==1'b1)
// begin
// o_Receiving <= 1'b0;
// o_RxER <= 1'b1;
// end else
// begin
// o_RxDV <= 1'b0;
// o_RxER <= 1'b0;
// end
// if(i3_Xmit!=`cXmitDATA) o_Invalid <= 1'b1;
// end
endcase
end
/src/mANCtrl.v
1,5 → 1,20
/*
Developed By Subtleware Corporation Pte Ltd 2011
Copyright � 2012 JeffLieu-lieumychuong@gmail.com
This file is part of SGMII-IP-Core.
SGMII-IP-Core is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
 
SGMII-IP-Core is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with SGMII-IP-Core. If not, see <http://www.gnu.org/licenses/>.
 
File :
Description :
Remarks : No Support for Next Page
97,7 → 112,7
else if(w_LinkTimerDone && (~w_AbiMatch||(r16_LpAdvAbility!=16'h0000)))
r8_State <= stIDLE_DTECT;
stIDLE_DTECT : if(w_IdleMatch && w_LinkTimerDone) r8_State <= stLINK_OK; else
if(w_IdleMatch && r16_LpAdvAbility==16'h0000) r8_State <= stAN_ENABLE;
if(w_AbiMatch && r16_LpAdvAbility==16'h0000) r8_State <= stAN_ENABLE;
stLINK_OK : if(w_AbiMatch) r8_State <= stAN_ENABLE;
stAN_DIS_LINKOK : r8_State <= stAN_DIS_LINKOK;
182,7 → 197,7
if(r2_AcknowlMatchCnt!=2'b11) r2_AcknowlMatchCnt<=r2_AcknowlMatchCnt+1;
//Consistency Match
//When the flag acknowledge match is about to be set
//If the bits are same as r16_AbilityReg , consistent
//If the bits are same as r16_LpAdvAbility , consistent
//Else Not consistent;
//Consistency match is set at the same time as Acknowledge match
if(r2_AcknowlMatchCnt==2'b10 && (i16_RxConfigReg[13:00] == r16_AbilityReg[13:00] && i16_RxConfigReg[15]==r16_AbilityReg[15]))
/src/mRegisters.v
1,5 → 1,20
/*
Developed By Subtleware Corporation Pte Ltd 2011
 
 
This file is part of SGMII-IP-Core.
SGMII-IP-Core is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
 
SGMII-IP-Core is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with SGMII-IP-Core. If not, see <http://www.gnu.org/licenses/>.
File :
Description :
Remarks :
/src/mSGMII.v
1,5 → 1,20
/*
Developed By Jeff Lieu (lieumychuong@gmail.com)
Copyright � 2012 JeffLieu-lieumychuong@gmail.com
 
This file is part of SGMII-IP-Core.
SGMII-IP-Core is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
 
SGMII-IP-Core is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with SGMII-IP-Core. If not, see <http://www.gnu.org/licenses/>.
 
File :
Description :
This core implements:
110,6 → 125,10
wire [20:00] w21_LinkTimer;
wire w_TxEN,w_TxER,w_RxER, w_RxDV;
wire [07:00] w8_RxD, w8_TxD;
wire w_BitSlip;
wire w_Invalid;//Not Used
wire w_TxEven;//Not Used
wire w_CurrentParity;
//MII Clock Gen
reg [6:0] r7_Cntr;
146,7 → 165,7
generate
genvar STAGE;
for(STAGE=0;STAGE<3;STAGE=STAGE+1)
begin
begin:PreCheck
assign w3_PreCheckIsComma[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b1 && r8_RxCodeGroup[STAGE]==`K28_5)?1'b1:1'b0;
assign w3_PreCheckIsTSet[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b1 && r8_RxCodeGroup[STAGE]==`K29_7)?1'b1:1'b0;
assign w3_PreCheckIsRSet[STAGE] = (r_RxCgInvalid[STAGE]==1'b0 && r_RxCgCtrl[STAGE]==1'b1 && r8_RxCodeGroup[STAGE]==`K23_7)?1'b1:1'b0;
193,7 → 212,7
.i32_WrData (i32_WrData),
.o32_RdData (o32_RdData),
.o_Ack (o_Ack),
.o_Stall (o_Stall),
.o_Stall (),
.io_Mdio (io_Mdio),
.i_Mdc (i_Mdc),
298,7 → 317,7
.o_RxDV (w_RxDV ),
.o_RxER (w_RxER ),
.o8_RxD (w8_RxD ),
.o_Invalid (o_Invalid),
.o_Invalid (w_Invalid),
.o_Receiving (w_Receiving),
.i_Clk (w_ClkSys),
.i_ARst_L (w_ARstLogic_L));
372,7 → 391,7
.i_RefClk125M (i_RefClk125M ),
.o_CoreClk (w_ClkSys ),
.i_GxBPwrDwn (w_GxBPowerDown ),
.i_XcverDigitalRst (~w_ARstLogic_L ),
.i_XcverDigitalRst (~i_ARstHardware_L ),
.o_PllLocked (w_PllLocked ),
.i_RxBitSlip (w_BitSlip ),
384,7 → 403,7
.i8_TxCodeGroup (w8_TxCode ),
.i_TxCodeValid (w_TxCodeValid ),
.i_TxCodeCtrl (w_TxCodeCtrl ),
.i_TxForceNegDisp (w_TxForceNegDisp ),
.i_TxForceNegDisp (1'b0 ),
.o_RunningDisparity (w_CurrentParity));
assign o_GMIIClk = w_ClkSys;
/src/mAltGX/mAltArriaVlvdsRx.v
37,37 → 37,44
`timescale 1 ps / 1 ps
// synopsys translate_on
module mAltArriaVlvdsRx (
pll_areset,
rx_channel_data_align,
rx_in,
rx_inclock,
rx_divfwdclk,
rx_locked,
rx_out,
rx_outclock);
 
input pll_areset;
input [0:0] rx_channel_data_align;
input [0:0] rx_in;
input rx_inclock;
output [0:0] rx_divfwdclk;
output rx_locked;
output [9:0] rx_out;
output rx_outclock;
 
wire sub_wire0;
wire [9:0] sub_wire1;
wire sub_wire2;
wire rx_locked = sub_wire0;
wire [9:0] rx_out = sub_wire1[9:0];
wire rx_outclock = sub_wire2;
wire [0:0] sub_wire0;
wire sub_wire1;
wire [9:0] sub_wire2;
wire sub_wire3;
wire [0:0] rx_divfwdclk = sub_wire0[0:0];
wire rx_locked = sub_wire1;
wire [9:0] rx_out = sub_wire2[9:0];
wire rx_outclock = sub_wire3;
 
altlvds_rx ALTLVDS_RX_component (
.rx_in (rx_in),
.rx_inclock (rx_inclock),
.pll_areset (pll_areset),
.rx_channel_data_align (rx_channel_data_align),
.rx_locked (sub_wire0),
.rx_out (sub_wire1),
.rx_outclock (sub_wire2),
.rx_divfwdclk (sub_wire0),
.rx_locked (sub_wire1),
.rx_out (sub_wire2),
.rx_outclock (sub_wire3),
.dpa_pll_cal_busy (),
.dpa_pll_recal (1'b0),
.pll_areset (1'b0),
.pll_phasecounterselect (),
.pll_phasedone (1'b1),
.pll_phasestep (),
80,7 → 87,6
.rx_data_align_reset (1'b0),
.rx_data_reset (1'b0),
.rx_deskew (1'b0),
.rx_divfwdclk (),
.rx_dpa_lock_reset (1'b0),
.rx_dpa_locked (),
.rx_dpaclock (1'b0),
96,7 → 102,7
defparam
ALTLVDS_RX_component.buffer_implementation = "RAM",
ALTLVDS_RX_component.cds_mode = "UNUSED",
ALTLVDS_RX_component.common_rx_tx_pll = "OFF",
ALTLVDS_RX_component.common_rx_tx_pll = "ON",
ALTLVDS_RX_component.data_align_rollover = 10,
ALTLVDS_RX_component.data_rate = "1250.0 Mbps",
ALTLVDS_RX_component.deserialization_factor = 10,
108,9 → 114,9
ALTLVDS_RX_component.enable_dpa_calibration = "ON",
ALTLVDS_RX_component.enable_dpa_fifo = "UNUSED",
ALTLVDS_RX_component.enable_dpa_initial_phase_selection = "OFF",
ALTLVDS_RX_component.enable_dpa_mode = "OFF",
ALTLVDS_RX_component.enable_dpa_mode = "ON",
ALTLVDS_RX_component.enable_dpa_pll_calibration = "OFF",
ALTLVDS_RX_component.enable_soft_cdr_mode = "OFF",
ALTLVDS_RX_component.enable_soft_cdr_mode = "ON",
ALTLVDS_RX_component.implement_in_les = "OFF",
ALTLVDS_RX_component.inclock_boost = 0,
ALTLVDS_RX_component.inclock_data_alignment = "EDGE_ALIGNED",
131,7 → 137,7
ALTLVDS_RX_component.registered_data_align_input = "UNUSED",
ALTLVDS_RX_component.registered_output = "ON",
ALTLVDS_RX_component.reset_fifo_at_first_lock = "UNUSED",
ALTLVDS_RX_component.rx_align_data_reg = "RISING_EDGE",
ALTLVDS_RX_component.rx_align_data_reg = "UNUSED",
ALTLVDS_RX_component.sim_dpa_is_negative_ppm_drift = "OFF",
ALTLVDS_RX_component.sim_dpa_net_ppm_variation = 0,
ALTLVDS_RX_component.sim_dpa_output_clock_phase_shift = 0,
156,7 → 162,7
// Retrieval info: PRIVATE: Deser_Factor NUMERIC "10"
// Retrieval info: PRIVATE: Dpll_Lock_Count NUMERIC "0"
// Retrieval info: PRIVATE: Dpll_Lock_Window NUMERIC "0"
// Retrieval info: PRIVATE: Enable_DPA_Mode STRING "OFF"
// Retrieval info: PRIVATE: Enable_DPA_Mode STRING "ON"
// Retrieval info: PRIVATE: Enable_FIFO_DPA_Channels NUMERIC "0"
// Retrieval info: PRIVATE: Ext_PLL STRING "OFF"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria V"
172,15 → 178,15
// Retrieval info: PRIVATE: Reg_InOut NUMERIC "1"
// Retrieval info: PRIVATE: Use_Cda_Reset NUMERIC "0"
// Retrieval info: PRIVATE: Use_Clock_Resc STRING "Dual-Regional clock"
// Retrieval info: PRIVATE: Use_Common_Rx_Tx_Plls NUMERIC "0"
// Retrieval info: PRIVATE: Use_Common_Rx_Tx_Plls NUMERIC "1"
// Retrieval info: PRIVATE: Use_Data_Align NUMERIC "1"
// Retrieval info: PRIVATE: Use_Lock NUMERIC "1"
// Retrieval info: PRIVATE: Use_Pll_Areset NUMERIC "0"
// Retrieval info: PRIVATE: Use_Pll_Areset NUMERIC "1"
// Retrieval info: PRIVATE: Use_Rawperror NUMERIC "0"
// Retrieval info: PRIVATE: Use_Tx_Out_Phase NUMERIC "0"
// Retrieval info: CONSTANT: BUFFER_IMPLEMENTATION STRING "RAM"
// Retrieval info: CONSTANT: CDS_MODE STRING "UNUSED"
// Retrieval info: CONSTANT: COMMON_RX_TX_PLL STRING "OFF"
// Retrieval info: CONSTANT: COMMON_RX_TX_PLL STRING "ON"
// Retrieval info: CONSTANT: clk_src_is_pll STRING "off"
// Retrieval info: CONSTANT: DATA_ALIGN_ROLLOVER NUMERIC "10"
// Retrieval info: CONSTANT: DATA_RATE STRING "1250.0 Mbps"
193,9 → 199,9
// Retrieval info: CONSTANT: ENABLE_DPA_CALIBRATION STRING "ON"
// Retrieval info: CONSTANT: ENABLE_DPA_FIFO STRING "UNUSED"
// Retrieval info: CONSTANT: ENABLE_DPA_INITIAL_PHASE_SELECTION STRING "OFF"
// Retrieval info: CONSTANT: ENABLE_DPA_MODE STRING "OFF"
// Retrieval info: CONSTANT: ENABLE_DPA_MODE STRING "ON"
// Retrieval info: CONSTANT: ENABLE_DPA_PLL_CALIBRATION STRING "OFF"
// Retrieval info: CONSTANT: ENABLE_SOFT_CDR_MODE STRING "OFF"
// Retrieval info: CONSTANT: ENABLE_SOFT_CDR_MODE STRING "ON"
// Retrieval info: CONSTANT: IMPLEMENT_IN_LES STRING "OFF"
// Retrieval info: CONSTANT: INCLOCK_BOOST NUMERIC "0"
// Retrieval info: CONSTANT: INCLOCK_DATA_ALIGNMENT STRING "EDGE_ALIGNED"
216,7 → 222,7
// Retrieval info: CONSTANT: REGISTERED_DATA_ALIGN_INPUT STRING "UNUSED"
// Retrieval info: CONSTANT: REGISTERED_OUTPUT STRING "ON"
// Retrieval info: CONSTANT: RESET_FIFO_AT_FIRST_LOCK STRING "UNUSED"
// Retrieval info: CONSTANT: RX_ALIGN_DATA_REG STRING "RISING_EDGE"
// Retrieval info: CONSTANT: RX_ALIGN_DATA_REG STRING "UNUSED"
// Retrieval info: CONSTANT: SIM_DPA_IS_NEGATIVE_PPM_DRIFT STRING "OFF"
// Retrieval info: CONSTANT: SIM_DPA_NET_PPM_VARIATION NUMERIC "0"
// Retrieval info: CONSTANT: SIM_DPA_OUTPUT_CLOCK_PHASE_SHIFT NUMERIC "0"
225,8 → 231,12
// Retrieval info: CONSTANT: USE_EXTERNAL_PLL STRING "OFF"
// Retrieval info: CONSTANT: USE_NO_PHASE_SHIFT STRING "ON"
// Retrieval info: CONSTANT: X_ON_BITSLIP STRING "ON"
// Retrieval info: USED_PORT: pll_areset 0 0 0 0 INPUT NODEFVAL "pll_areset"
// Retrieval info: CONNECT: @pll_areset 0 0 0 0 pll_areset 0 0 0 0
// Retrieval info: USED_PORT: rx_channel_data_align 0 0 1 0 INPUT NODEFVAL "rx_channel_data_align[0..0]"
// Retrieval info: CONNECT: @rx_channel_data_align 0 0 1 0 rx_channel_data_align 0 0 1 0
// Retrieval info: USED_PORT: rx_divfwdclk 0 0 1 0 OUTPUT NODEFVAL "rx_divfwdclk[0..0]"
// Retrieval info: CONNECT: rx_divfwdclk 0 0 1 0 @rx_divfwdclk 0 0 1 0
// Retrieval info: USED_PORT: rx_in 0 0 1 0 INPUT NODEFVAL "rx_in[0..0]"
// Retrieval info: CONNECT: @rx_in 0 0 1 0 rx_in 0 0 1 0
// Retrieval info: USED_PORT: rx_inclock 0 0 0 0 INPUT NODEFVAL "rx_inclock"
/src/mAltGX/mAltArriaVlvdsTx.v
37,28 → 37,26
`timescale 1 ps / 1 ps
// synopsys translate_on
module mAltArriaVlvdsTx (
pll_areset,
tx_in,
tx_inclock,
tx_coreclock,
tx_out);
 
input pll_areset;
input [9:0] tx_in;
input tx_inclock;
output tx_coreclock;
output [0:0] tx_out;
 
wire sub_wire0;
wire [0:0] sub_wire1;
wire tx_coreclock = sub_wire0;
wire [0:0] tx_out = sub_wire1[0:0];
wire [0:0] sub_wire0;
wire [0:0] tx_out = sub_wire0[0:0];
 
altlvds_tx ALTLVDS_TX_component (
.pll_areset (pll_areset),
.tx_in (tx_in),
.tx_inclock (tx_inclock),
.tx_coreclock (sub_wire0),
.tx_out (sub_wire1),
.pll_areset (1'b0),
.tx_out (sub_wire0),
.sync_inclock (1'b0),
.tx_coreclock (),
.tx_data_reset (1'b0),
.tx_enable (1'b1),
.tx_locked (),
67,7 → 65,7
.tx_syncclock (1'b0));
defparam
ALTLVDS_TX_component.center_align_msb = "UNUSED",
ALTLVDS_TX_component.common_rx_tx_pll = "ON",
ALTLVDS_TX_component.common_rx_tx_pll = "OFF",
ALTLVDS_TX_component.coreclock_divide_by = 1,
ALTLVDS_TX_component.data_rate = "1250.0 Mbps",
ALTLVDS_TX_component.deserialization_factor = 10,
93,7 → 91,7
ALTLVDS_TX_component.pll_self_reset_on_loss_lock = "OFF",
ALTLVDS_TX_component.preemphasis_setting = 0,
ALTLVDS_TX_component.refclk_frequency = "125.000000 MHz",
ALTLVDS_TX_component.registered_input = "TX_CORECLK",
ALTLVDS_TX_component.registered_input = "TX_CLKIN",
ALTLVDS_TX_component.use_external_pll = "OFF",
ALTLVDS_TX_component.use_no_phase_shift = "ON",
ALTLVDS_TX_component.vod_setting = 0,
106,9 → 104,9
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: CNX_CLOCK_CHOICES STRING "tx_coreclock"
// Retrieval info: PRIVATE: CNX_CLOCK_CHOICES STRING "tx_inclock"
// Retrieval info: PRIVATE: CNX_CLOCK_MODE NUMERIC "0"
// Retrieval info: PRIVATE: CNX_COMMON_PLL NUMERIC "1"
// Retrieval info: PRIVATE: CNX_COMMON_PLL NUMERIC "0"
// Retrieval info: PRIVATE: CNX_DATA_RATE STRING "1250.0"
// Retrieval info: PRIVATE: CNX_DESER_FACTOR NUMERIC "10"
// Retrieval info: PRIVATE: CNX_EXT_PLL STRING "OFF"
115,11 → 113,11
// Retrieval info: PRIVATE: CNX_LE_SERDES STRING "OFF"
// Retrieval info: PRIVATE: CNX_NUM_CHANNEL NUMERIC "1"
// Retrieval info: PRIVATE: CNX_OUTCLOCK_DIVIDE_BY NUMERIC "1"
// Retrieval info: PRIVATE: CNX_PLL_ARESET NUMERIC "0"
// Retrieval info: PRIVATE: CNX_PLL_ARESET NUMERIC "1"
// Retrieval info: PRIVATE: CNX_PLL_FREQ STRING "125.000000"
// Retrieval info: PRIVATE: CNX_PLL_PERIOD STRING "8.000"
// Retrieval info: PRIVATE: CNX_REG_INOUT NUMERIC "1"
// Retrieval info: PRIVATE: CNX_TX_CORECLOCK STRING "ON"
// Retrieval info: PRIVATE: CNX_TX_CORECLOCK STRING "OFF"
// Retrieval info: PRIVATE: CNX_TX_LOCKED STRING "OFF"
// Retrieval info: PRIVATE: CNX_TX_OUTCLOCK STRING "OFF"
// Retrieval info: PRIVATE: CNX_USE_CLOCK_RESC STRING "Regional clock"
130,7 → 128,7
// Retrieval info: PRIVATE: pINCLOCK_PHASE_SHIFT STRING "0.00"
// Retrieval info: PRIVATE: pOUTCLOCK_PHASE_SHIFT STRING "0.00"
// Retrieval info: CONSTANT: CENTER_ALIGN_MSB STRING "UNUSED"
// Retrieval info: CONSTANT: COMMON_RX_TX_PLL STRING "ON"
// Retrieval info: CONSTANT: COMMON_RX_TX_PLL STRING "OFF"
// Retrieval info: CONSTANT: CORECLOCK_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: clk_src_is_pll STRING "off"
// Retrieval info: CONSTANT: DATA_RATE STRING "1250.0 Mbps"
157,12 → 155,12
// Retrieval info: CONSTANT: PLL_SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: PREEMPHASIS_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: REFCLK_FREQUENCY STRING "125.000000 MHz"
// Retrieval info: CONSTANT: REGISTERED_INPUT STRING "TX_CORECLK"
// Retrieval info: CONSTANT: REGISTERED_INPUT STRING "TX_CLKIN"
// Retrieval info: CONSTANT: USE_EXTERNAL_PLL STRING "OFF"
// Retrieval info: CONSTANT: USE_NO_PHASE_SHIFT STRING "ON"
// Retrieval info: CONSTANT: VOD_SETTING NUMERIC "0"
// Retrieval info: USED_PORT: tx_coreclock 0 0 0 0 OUTPUT NODEFVAL "tx_coreclock"
// Retrieval info: CONNECT: tx_coreclock 0 0 0 0 @tx_coreclock 0 0 0 0
// Retrieval info: USED_PORT: pll_areset 0 0 0 0 INPUT NODEFVAL "pll_areset"
// Retrieval info: CONNECT: @pll_areset 0 0 0 0 pll_areset 0 0 0 0
// Retrieval info: USED_PORT: tx_in 0 0 10 0 INPUT NODEFVAL "tx_in[9..0]"
// Retrieval info: CONNECT: @tx_in 0 0 10 0 tx_in 0 0 10 0
// Retrieval info: USED_PORT: tx_inclock 0 0 0 0 INPUT NODEFVAL "tx_inclock"
/src/mAltGX/mAltA5GXlvds.v
26,8 → 26,10
wire [9:0] w10_rxdata;
wire [9:0] w10_txdatalocal;
wire [9:0] w10_rxdatalocal;
wire w_RxKErr,w_RxRdErr;
wire w_TxClk;
mAlt8b10benc u8b10bEnc(
/*mAlt8b10benc u8b10bEnc(
.clk (o_CoreClk),
.reset_n (~i_XcverDigitalRst),
.idle_ins (~i_TxCodeValid),
40,9 → 42,19
.dataout (w10_txdatalocal),
.valid (),
.rdout (o_RunningDisparity),
.rdcascade ());
.rdcascade ());*/
mEnc8b10bMem u8b10bEnc(
.i8_Din (i8_TxCodeGroup), //HGFEDCBA
.i_Kin (i_TxCodeCtrl),
.i_ForceDisparity (i_TxForceNegDisp),
.i_Disparity (~i_TxForceNegDisp), //1 Is negative, 0 is positive
.o10_Dout (w10_txdata), //abcdeifghj
.o_Rd (o_RunningDisparity),
.o_KErr (),
.i_Clk (o_CoreClk),
.i_ARst_L (~i_XcverDigitalRst));
mAlt8b10bdec u8b10bDec(
/*mAlt8b10bdec u8b10bDec(
.clk (o_CoreClk),
.reset_n (~i_XcverDigitalRst),
.idle_del (),
56,10 → 68,23
.kerr (w_RxKErr),
.rdcascade (),
.rdout (),
.rderr (w_RxRdErr));
.rderr (w_RxRdErr));*/
mDec8b10bMem u8b10bDec(
.o8_Dout (o8_RxCodeGroup), //HGFEDCBA
.o_Kout (o_RxCodeCtrl),
.o_DErr (),
.o_KErr (w_RxKErr),
.o_DpErr (w_RxRdErr),
.i_ForceDisparity (1'b0),
.i_Disparity (1'b0),
.i10_Din (w10_rxdata), //abcdeifghj
.o_Rd (),
.i_Clk (o_CoreClk),
.i_ARst_L (~i_XcverDigitalRst));
assign o_RxCodeInvalid = w_RxKErr|w_RxRdErr;
assign o_SignalDetect = w_RxDataValid|o_RxCodeCtrl;
assign o_SignalDetect = (~o_RxCodeInvalid)|o_RxCodeCtrl;
mAltArriaVlvdsRx ulvdsrx (
.rx_channel_data_align (i_RxBitSlip),
67,13 → 92,16
.rx_inclock (i_RefClk125M),
.rx_out (w10_rxdata),
.rx_locked (o_PllLocked),
.rx_outclock (o_CoreClk));
//.rx_outclock (o_CoreClk),
.rx_divfwdclk (o_CoreClk),
.pll_areset (i_XcverDigitalRst));
mAltArriaVlvdsTx ulvdstx(
.tx_in (w10_txdata),
.tx_inclock (i_RefClk125M),
.tx_coreclock (w_TxClk),
.tx_out (o_SerTx));
.tx_inclock (o_CoreClk),
//.tx_coreclock (w_TxClk),
.tx_out (o_SerTx),
.pll_areset(i_XcverDigitalRst));
function [9:0] bitreverse ;
85,8 → 113,8
end
endfunction
assign w10_txdata = bitreverse(w10_txdatalocal);
assign w10_rxdatalocal = bitreverse(w10_rxdata);
//assign w10_txdata = bitreverse(w10_txdatalocal);
//assign w10_rxdatalocal = bitreverse(w10_rxdata);
// mAltRateAdapter uRxAdapter(
// .data (w10_txdatalocal),
// .rdclk (w_TxClk),
/src/mAltGX/mAltArriaVlvdsRx.ppf
2,9 → 2,11
<!DOCTYPE pinplan>
<pinplan intended_family="Arria V" variation_name="mAltArriaVlvdsRx" megafunction_name="ALTLVDS_RX" specifies="all_ports">
<global>
<pin name="pll_areset" direction="input" scope="external" />
<pin name="rx_channel_data_align[0..0]" direction="input" scope="external" />
<pin name="rx_in[0..0]" direction="input" scope="external" />
<pin name="rx_inclock" direction="input" scope="external" />
<pin name="rx_divfwdclk[0..0]" direction="output" scope="external" />
<pin name="rx_locked" direction="output" scope="external" />
<pin name="rx_out[9..0]" direction="output" scope="external" />
<pin name="rx_outclock" direction="output" scope="external" />
/src/mAltGX/mAltArriaVlvdsTx.ppf
2,9 → 2,9
<!DOCTYPE pinplan>
<pinplan intended_family="Arria V" variation_name="mAltArriaVlvdsTx" megafunction_name="ALTLVDS_TX" specifies="all_ports">
<global>
<pin name="pll_areset" direction="input" scope="external" />
<pin name="tx_in[9..0]" direction="input" scope="external" />
<pin name="tx_inclock" direction="input" scope="external" />
<pin name="tx_coreclock" direction="output" scope="external" />
<pin name="tx_out[0..0]" direction="output" scope="external" />
 
</global>
/src/mRateAdapter.v
1,5 → 1,20
/*
Developed By Subtleware Corporation Pte Ltd 2011
 
This file is part of SGMII-IP-Core.
SGMII-IP-Core is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
 
SGMII-IP-Core is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with SGMII-IP-Core. If not, see <http://www.gnu.org/licenses/>.
 
File :
Description :
Remarks :
/src/SGMIIDefs.v
1,3 → 1,32
/*
 
This file is part of SGMII-IP-Core.
SGMII-IP-Core is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
 
SGMII-IP-Core is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
 
You should have received a copy of the GNU General Public License
along with SGMII-IP-Core. If not, see <http://www.gnu.org/licenses/>.
 
 
File :
Description :
 
Remarks :
 
Revision :
Date Author Description
 
*/
 
`define cSystemClkPeriod 8
 
`define cXmitCONFIG 3'b010
/sim/Testbench_AltGXB_SGMII1000Mbps.sv
103,14 → 103,15
$display("------------------------------------");
$display("-------Subtleware Ltd Pte 2012------");
$display("--Testing SGMII in SGMII 1000Gb Mode------");
$display("------------------------------------");
u0WishboneMstr.tsk_Read((10<<2),r16_CoreVersion);
$display("---Core Version : %x", r16_CoreVersion);
$display("------------------------------------");
tstcfg_TxPktCnt = 0;
tstcfg_RxPktCnt = 0;
r_Reset_L <= 1'b0;
#1000;
r_Reset_L <= 1'b1;
#1000;
u0WishboneMstr.tsk_Read((10<<2),r16_CoreVersion);
$display("---Core Version : %x", r16_CoreVersion);
tsk_Setup();
end
/sim/Sim_SGMII1000Mblvds.do
1,7 → 1,7
 
set incDir {../src+../src/mAltGX}
set srcDir {../src}
set SrcFiles {mANCtrl.v mReceive.v mTransmit.v mSyncCtrl.v mSGMII.v mXcver.v mSyncFifo.v mRegisters.v mClkBuf.v mRateAdapter.v}
set SrcFiles {mANCtrl.v mReceive.v mTransmit.v mSyncCtrl.v mSGMII.v mXcver.v mSyncFifo.v mRegisters.v mClkBuf.v mRateAdapter.v mEnc8b10bMem.v mDec8b10bMem.v}
set BfmDir {./BFMs}
set BfmFiles {mWishboneMstr.v}
foreach src $SrcFiles {
/sim/Testbench_AltGXB_1000BaseX.sv
103,14 → 103,14
$display("------------------------------------");
$display("-------Subtleware Ltd Pte 2012------");
$display("--Testing SGMII in 1000Gb Mode------");
$display("------------------------------------");
u0WishboneMstr.tsk_Read((10<<2),r16_CoreVersion);
$display("---Core Version : %x", r16_CoreVersion);
$display("------------------------------------");
tstcfg_TxPktCnt = 0;
tstcfg_RxPktCnt = 0;
r_Reset_L <= 1'b0;
#1000;
r_Reset_L <= 1'b1;
u0WishboneMstr.tsk_Read((10<<2),r16_CoreVersion);
$display("---Core Version : %x", r16_CoreVersion);
tsk_Setup();
end

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