URL
https://opencores.org/ocsvn/sgmii/sgmii/trunk
Subversion Repositories sgmii
Compare Revisions
- This comparison shows the changes necessary to convert path
/sgmii/trunk
- from Rev 2 to Rev 3
- ↔ Reverse comparison
Rev 2 → Rev 3
/src/mReceive.v
146,7 → 146,7
stWAIT_FOR_K: if(i_IsComma && i_RxEven) r21_NxtState <= stRX_K; else r21_NxtState<=stWAIT_FOR_K; |
stRX_K : if(wSUDID21_5||wSUDID2_2) |
r21_NxtState <= stRX_CB; else |
if((!i_RxCodeInvalid) && i_RxCodeCtrl && i3_Xmit!=`cXmitDATA) |
if((!i_RxCodeInvalid) && (!i_RxCodeCtrl) && i3_Xmit!=`cXmitDATA) |
r21_NxtState <= stRX_INVALID; else |
if(((!i_RxCodeInvalid) && (!i_RxCodeCtrl) && i3_Xmit!=`cXmitDATA && i8_RxCodeGroupIn!=`D21_5 && i8_RxCodeGroupIn!=`D2_2)|| |
((!i_RxCodeInvalid) && i3_Xmit==`cXmitDATA && ((i8_RxCodeGroupIn!=`D21_5 && i8_RxCodeGroupIn!=`D2_2 && (!i_RxCodeCtrl))||i_RxCodeCtrl))) |
/src/mRegisters.v
134,7 → 134,7
assign o16_LcAdvAbility = w16_LcAdvAbility; |
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assign w16_LcAdvAbility = (w_UseAsSGMII==1'b0)?({1'b0,i16_TxConfigReg[15],r16_CtrlReg4[13:12],3'b000,r16_CtrlReg4[8:7],2'b01,5'b00000})://1000-X mode |
((w_SGMII_PHY==1'b1)?({i_PhyLink,i16_TxConfigReg[15],1'b0,i_PhyDuplex,i2_PhySpeed,10'h1}): |
((w_SGMII_PHY==1'b1)?({i_PhyLink,i16_TxConfigReg[15],1'b0,(i_PhyDuplex|r16_CtrlReg4[12]),(i2_PhySpeed|r16_CtrlReg4[11:10]),10'h1})://SGMII mode - PHY Side |
({1'b0,i16_TxConfigReg[15],1'b0,3'b000,10'h1}));//SGMII mode - MAC Side |
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assign w16_StatusReg1 = {9'h0,i_ANComplete,2'b01,i_SyncStatus,2'b0}; |
/src/mSGMII.v
1,5 → 1,5
/* |
Developed By Subtleware Corporation Pte Ltd 2011 |
Developed By Jeff Lieu (lieumychuong@gmail.com) |
File : |
Description : |
This core implements: |
335,6 → 335,7
.i_Clk (w_ClkSys ), |
.i_ARst_L (w_ARstLogic_L )); |
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assign w_SignalDetect=~w_RxCodeInvalid; |
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mXcver u0Xcver( |
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348,7 → 349,7
.i_XcverDigitalRst (~w_ARstLogic_L ), |
.o_PllLocked (w_PllLocked ), |
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.o_SignalDetect (w_SignalDetect ), |
.o_SignalDetect (), |
.o8_RxCodeGroup (w8_RxCode ), |
.o_RxCodeInvalid (w_RxCodeInvalid ), |
.o_RxCodeCtrl (w_RxCodeCtrl ), |
/src/SGMIIDefs.v
18,4 → 18,14
`define cReg4Default 16'h0000 |
`define cReg0Default 16'h0000 |
`define cRegXDefault 16'h0000 |
`define cRegLinkTimerDefault (10_000_000/8) |
`define cRegLinkTimerDefault (10_000_000/8) |
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`define cLcAbility_FD 16'h0020 |
`define cLcAbility_HD 16'h0040 |
`define cLcAbility_PS1 16'h0080 |
`define cLcAbility_PS2 16'h0100 |
`define cLcAbility_RF1 16'h1000 |
`define cLcAbility_RF2 16'h2000 |
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