Subversion Repositories sha256_hash_core

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doc/src/GV_SHA256_msg_sch.jpg Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: doc/src/GV_SHA256_msg_sch.png =================================================================== Cannot display: file marked as a binary type. svn:mime-type = application/octet-stream Index: doc/src/GV_SHA256_msg_sch.png =================================================================== --- doc/src/GV_SHA256_msg_sch.png (nonexistent) +++ doc/src/GV_SHA256_msg_sch.png (revision 9)

doc/src/GV_SHA256_msg_sch.png Property changes : Added: svn:mime-type ## -0,0 +1 ## +application/octet-stream \ No newline at end of property Index: syn/sha256/isim.log =================================================================== --- syn/sha256/isim.log (revision 8) +++ syn/sha256/isim.log (nonexistent) @@ -1,20 +0,0 @@ -ISim log file -Running: Z:\Dropbox\develop\fpga\sha256_hash_core\sha256_hash_core\trunk\syn\sha256\testbench_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb Z:/Dropbox/develop/fpga/sha256_hash_core/sha256_hash_core/trunk/syn/sha256/testbench_isim_beh.wdb -ISim P.20131013 (signature 0x7708f090) -WARNING: A WEBPACK license was found. -WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. -WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version. -This is a Lite version of ISim. -Time resolution is 1 ps -# onerror resume -# wave add / -# run all -Simulator is doing circuit initialization process. -at 0 ps, Instance /testbench/Inst_sha_256_dut/Inst_sha256_kt_rom/ : Warning: NUMERIC_STD.TO_INTEGER: metavalue detected, returning 0 -Finished circuit initialization process. - -** Failure:End Simulation -User(VHDL) Code Called Simulation Stop -In process sha256_test.vhd:tb1 - -INFO: Simulator is stopped. Index: syn/sha256/gv_sha256_summary.html =================================================================== --- syn/sha256/gv_sha256_summary.html (revision 8) +++ syn/sha256/gv_sha256_summary.html (nonexistent) @@ -1,80 +0,0 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -

gv_sha256 Project Status
Project File:	sha256.xise	Parser Errors:
Module Name:	gv_sha256	Implementation State:	New
Target Device:	xc6slx45-2csg324	Errors:
Product Version:	ISE 14.7	Warnings:
Design Goal:	Timing Performance	Routing Results:	-
Design Strategy:	SmartXplorer - mapruntimect3	Timing Constraints:
Environment:		Final Timing Score:

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Detailed Reports						[-]
Report Name	Status	Generated	Errors	Warnings	Infos
Synthesis Report
Translation Report
Map Report
Place and Route Report
Power Report
Post-PAR Static Timing Report
Bitgen Report

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Secondary Reports			[-]
Report Name	Status	Generated
ISIM Simulator Log	Out of Date	Fri Jul 22 12:10:37 2016

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Date Generated: 07/22/2016 - 12:10:43 - \ No newline at end of file Index: syn/sha256/gv_sha256.vhd =================================================================== --- syn/sha256/gv_sha256.vhd (revision 8) +++ syn/sha256/gv_sha256.vhd (revision 9) @@ -36,29 +36,29 @@ -- It is used in the GridVortex CyberSec IP, as a base for the fused HMAC-SHA256, HKDF, HMAC-SHA256-DRBG, and the SP-800 TRNG Entropy Source. -- ------------------------------ COPYRIGHT NOTICE ----------------------------------------------------------------------- --- --- This file is part of the SHA256 HASH CORE project http://opencores.org/project,sha256_hash_core --- --- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gridvortex.com, jonnydoin@gmail.com --- --- Copyright (C) 2016 Jonny Doin --- ----------------------------- --- --- This source file may be used and distributed without restriction provided that this copyright statement is not --- removed from the file and that any derivative work contains the original copyright notice and the associated --- disclaimer. --- --- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser --- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or --- (at your option) any later version. --- --- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied --- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more --- details. --- --- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download --- it from http://www.gnu.org/licenses/lgpl.txt --- +-- +-- This file is part of the SHA256 HASH CORE project http://opencores.org/project,sha256_hash_core +-- +-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gridvortex.com, jonnydoin@gmail.com +-- +-- Copyright (C) 2016 Jonny Doin +-- ----------------------------- +-- +-- This source file may be used and distributed without restriction provided that this copyright statement is not +-- removed from the file and that any derivative work contains the original copyright notice and the associated +-- disclaimer. +-- +-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser +-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or +-- (at your option) any later version. +-- +-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied +-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more +-- details. +-- +-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download +-- it from http://www.gnu.org/licenses/lgpl.txt +-- ------------------------------ REVISION HISTORY ----------------------------------------------------------------------- -- -- 2016/05/22 v0.01.0010 [JD] started development. design of blocks and port interfaces. @@ -68,6 +68,7 @@ -- 2016/06/07 v0.01.0105 [JD] verification against all NIST-FIPS-180-4 test vectors passed. -- 2016/06/11 v0.01.0105 [JD] verification against NIST-SHA2_Additional test vectors #1 to #10 passed. -- 2016/06/11 v0.01.0110 [JD] optimized controller states, reduced 2 clocks per block, added lookahead register feedback. +-- 2016/09/25 v0.01.0220 [JD] changed 'di_ack_i' name to 'di_wr_i', and changed semantics to 'data write'. -- -- ----------------------------------------------------------------------------------------------------------------------- @@ -89,7 +90,7 @@ end_i : in std_logic := 'U'; -- marks end of last block data input -- handshake di_req_o : out std_logic; -- requests data input for next word - di_ack_i : in std_logic := 'U'; -- high for di_i valid, low for hold + di_wr_i : in std_logic := 'U'; -- high for di_i valid, low for hold error_o : out std_logic; -- signalizes error. output data is invalid do_valid_o : out std_logic; -- when high, the output is valid -- 256bit output registers @@ -177,7 +178,7 @@ clk_i => clk_i, ce_i => ce_i, bytes_i => bytes_i, - ack_i => di_ack_i, + wr_i => di_wr_i, start_i => start_i, end_i => end_i, error_i => error_pad, Index: syn/sha256/sha256_test.vhd =================================================================== --- syn/sha256/sha256_test.vhd (revision 8) +++ syn/sha256/sha256_test.vhd (revision 9) @@ -13,6 +13,8 @@ -- and tests the GV_SHA256 engine with the NIST SHA256 test vectors, including the additional NIST test vectors up to the -- 1 million chars. -- +-- The logic implements a fast engine, with 66 cycles per 512-bit block. +-- -- The following waveforms describe the operation of the engine control signals for message start, update and end. -- -- BEGIN BLOCK (1st block) @@ -35,7 +37,7 @@ -- __ _ _ _ _____________________________________________________________________________________________________ -- di_req_o __ _ _ _\_____/ \_______________... -- 'di_req_o' asserted during data input -- ___________________________________________ _________________________________________________________ --- ack_i __________/____/ \_____/ \_____________... -- 'ack_i' can hold the core for slow data +-- wr_i __________/____/ \_____/ \_____________... -- 'wr_i' can hold the core for slow data -- __________ _________ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ ______ ______________... -- di_i __________\___\_W0__\__W1_\__W2_\__W3_\__W4_\__W5_\\\\\\\__W6_\__W7_\__W8_\__W9_\_W10_\_W11_\_W12_\_W13_\_W14_\_W15__\______X_______... -- user words on 'di_i' are latched on 'clk_i' rising edge -- ____________________ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ _____________________... @@ -63,7 +65,7 @@ -- _____________________________________________________________________________________________________ -- di_req_o ____________________/ \___... -- 'di_req_o' asserted during data input -- ___________________________________________________ _________________________________________________________ --- ack_i ________/__________/ \_____/ \_... -- 'ack_i' can hold the core for slow data +-- wr_i ________/__________/ \_____/ \_... -- 'wr_i' can hold the core for slow data -- _________________ _ ______ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ _____ ____... -- di_i _________________\\\___W0_\__W1_\__W2_\__W3_\__W4_\__W5_\\\\\\\\_W6_\__W7_\__W8_\__W9_\_W10_\_W11_\_W12_\_W13_\_W14_\_W15_\\_X_... -- user words on 'di_i' are latched on 'clk_i' rising edge -- @@ -81,7 +83,7 @@ -- _______ _ _ ___________________________________________________________________________________________________________ -- di_req_o ________/ \___... -- 'di_req_o' asserted during data input -- __________________________________________________ _____________________________________________ --- ack_i ________________ _ _ ______/ \_____/ \_... -- 'ack_i' valid on rising edge of 'clk_i' +-- wr_i ________________ _ _ ______/ \_____/ \_... -- 'wr_i' valid on rising edge of 'clk_i' -- ________________ _ _ ___________ _____ _____ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ ____... -- di_i ________________ _ _ ______\_W0_\__W1_\__W2_\__W3_\__W4_\__W5_\__W6_\__W7_\\\\_____W8_\__W9_\_W10_\_W11_\_W12_\_W13_\_W14_\_W15_\__Z_... -- user words on 'di_i' are latched on 'clk_i' rising edge -- @@ -104,7 +106,7 @@ -- ___________________________________ __________ -- di_req_o ________/ \__________ _ _ ___________________ _ _ ________________________________/ ... -- 'di_req_o' asserted during data input -- ______________________________________ _________ --- ack_i _________/ \\\______ _ _ ___________________ _ _ _________________________________/ ... -- 'ack_i' can hold the core for slow data +-- wr_i _________/ \\\______ _ _ ___________________ _ _ _________________________________/ ... -- 'wr_i' can hold the core for slow data -- ______________ _____ _____ _____ _____ _____ __________ _ _ ___________________ _ _ ______________________________________ ____... -- di_i _________\_W0_\__W1_\__W2_\__W3_\__W4_\__W5_\__________ _ _ ___________________ _ _ _________________________________\_W0_\__W1... -- words after the end_i assertion are ignored -- __ _____ _____ _____ _____ _____ _____ _____ _____ ____ _ ____ _____ _____ ____ _ _ ______________________________________ ____ @@ -149,7 +151,7 @@ -- _________________ __________ -- di_req_o \__________ _ _ ___________________ _ _ _____________ _ _ __________________________/ ... -- 'di_req_o' asserted on rising edge of 'clk_i' -- ____________________ _________ --- ack_i \\\_______ _ _ ___________________ _ _ _____________ _ _ ___________________________/ ... -- 'ack_i' valid on rising edge of 'clk_i' +-- wr_i \\\_______ _ _ ___________________ _ _ _____________ _ _ ___________________________/ ... -- 'wr_i' valid on rising edge of 'clk_i' -- _____ _____ _____ __________ _ _ ___________________ _ _ _____________ _ _ ________________________________ ____... -- di_i _W13_\_W14_\_W15_\__________ _ _ ___________________ _ _ _____________ _ _ ___________________________\_W0_\__W1... -- words after the end_i assertion are ignored -- _____ _____ _____ _____ ____ _ ____ _____ _____ ____ _ _ ________ ____ _ ____ _____ _______________________ ____ @@ -194,6 +196,7 @@ -- 2016/06/11 v0.01.0105 [JD] verification against NIST-SHA2_Additional test vectors #1 to #10 passed. -- 2016/06/11 v0.01.0110 [JD] optimized controller states, reduced 2 clocks per block. -- 2016/06/18 v0.01.0120 [JD] implemented error detection on 'bytes_i' input. +-- 2016/09/25 v0.01.0220 [JD] changed 'di_ack_i' name to 'di_wr_i', and changed semantics to 'data write'. -- ----------------------------------------------------------------------------------------------------------------------- -- TODO @@ -238,7 +241,7 @@ signal dut_end : std_logic; -- marks end of last block data input -- handshake signal dut_di_req : std_logic; -- requests data input for next word - signal dut_di_ack : std_logic; -- high for di_i valid, low for hold + signal dut_di_wr : std_logic; -- high for di_i write, low for hold signal dut_error : std_logic; -- signalizes error. output data is invalid signal dut_do_valid : std_logic; -- when high, the output is valid -- 256bit output registers @@ -273,7 +276,7 @@ end_i => dut_end, -- handshake di_req_o => dut_di_req, - di_ack_i => dut_di_ack, + di_wr_i => dut_di_wr, error_o => dut_error, do_valid_o => dut_do_valid, -- 256bit output registers @@ -319,7 +322,7 @@ dut_bytes <= b"00"; dut_start <= '0'; dut_end <= '0'; - dut_di_ack <= '0'; + dut_di_wr <= '0'; wait until pclk'event and pclk = '1'; dut_ce <= '1'; dut_start <= '1'; @@ -327,11 +330,14 @@ dut_bytes <= b"11"; wait until pclk'event and pclk = '1'; dut_start <= '0'; - wait until dut_di_req = '1'; - dut_di_ack <= '1'; + dut_di_wr <= '1'; + if dut_di_req = '0' then + wait until dut_di_req = '1'; + end if; dut_end <= '1'; wait until pclk'event and pclk = '1'; dut_end <= '0'; + dut_di_wr <= '0'; if dut_error /= '1' and dut_do_valid /= '1' then while dut_error /= '1' and dut_do_valid /= '1' loop wait until pclk'event and pclk = '1'; @@ -360,7 +366,7 @@ dut_bytes <= b"00"; dut_start <= '0'; dut_end <= '0'; - dut_di_ack <= '0'; + dut_di_wr <= '0'; wait until pclk'event and pclk = '1'; dut_ce <= '1'; dut_start <= '1'; @@ -367,9 +373,11 @@ wait until pclk'event and pclk = '1'; -- 'begin' pulse minimum width is one clock wait for 25 ns; -- TEST: stretch 'begin' pulse dut_start <= '0'; - wait until dut_di_req = '1'; + if dut_di_req = '0' then + wait until dut_di_req = '1'; + end if; wait until pclk'event and pclk = '1'; - dut_di_ack <= '1'; + dut_di_wr <= '1'; dut_bytes <= b"00"; dut_di <= x"61626364"; wait until pclk'event and pclk = '1'; @@ -384,11 +392,11 @@ dut_di <= x"66676869"; wait until pclk'event and pclk = '1'; dut_di <= x"6768696A"; - dut_di_ack <= '0'; + dut_di_wr <= '0'; wait until pclk'event and pclk = '1'; wait until pclk'event and pclk = '1'; wait until pclk'event and pclk = '1'; - dut_di_ack <= '1'; -- TEST: slow inputs with 'ack' handshake + dut_di_wr <= '1'; -- TEST: slow inputs with 'ack' handshake wait until pclk'event and pclk = '1'; dut_di <= x"68696A6B"; wait until pclk'event and pclk = '1'; @@ -409,6 +417,7 @@ dut_bytes <= b"01"; -- TEST: change 'bytes' value after END wait for 75 ns; -- TEST: stretch 'end' pulse dut_end <= '0'; + dut_di_wr <= '0'; if dut_error /= '1' and dut_do_valid /= '1' then while dut_error /= '1' and dut_do_valid /= '1' loop wait until pclk'event and pclk = '1'; @@ -425,16 +434,18 @@ dut_bytes <= b"00"; dut_start <= '0'; dut_end <= '0'; - dut_di_ack <= '0'; + dut_di_wr <= '0'; wait until pclk'event and pclk = '1'; dut_ce <= '1'; dut_start <= '1'; dut_di <= x"61626364"; dut_bytes <= b"00"; - dut_di_ack <= '1'; wait until pclk'event and pclk = '1'; -- 'begin' pulse minimum width is one clock dut_start <= '0'; - wait until dut_di_req = '1'; + dut_di_wr <= '1'; + if dut_di_req = '0' then + wait until dut_di_req = '1'; + end if; wait until pclk'event and pclk = '1'; dut_di <= x"62636465"; wait until pclk'event and pclk = '1'; @@ -464,6 +475,7 @@ dut_end <= '1'; wait until pclk'event and pclk = '1'; -- 'end' pulse minimum width is one clock dut_end <= '0'; + dut_di_wr <= '0'; if dut_error /= '1' and dut_do_valid /= '1' then while dut_error /= '1' and dut_do_valid /= '1' loop wait until pclk'event and pclk = '1'; @@ -493,7 +505,7 @@ dut_bytes <= b"00"; dut_start <= '0'; dut_end <= '0'; - dut_di_ack <= '0'; + dut_di_wr <= '0'; wait until pclk'event and pclk = '1'; dut_ce <= '1'; dut_start <= '1'; @@ -501,11 +513,14 @@ dut_bytes <= b"01"; wait until pclk'event and pclk = '1'; dut_start <= '0'; - wait until dut_di_req = '1'; - dut_di_ack <= '1'; + dut_di_wr <= '1'; + if dut_di_req = '0' then + wait until dut_di_req = '1'; + end if; dut_end <= '1'; wait until pclk'event and pclk = '1'; dut_end <= '0'; + dut_di_wr <= '0'; if dut_error /= '1' and dut_do_valid /= '1' then while dut_error /= '1' and dut_do_valid /= '1' loop wait until pclk'event and pclk = '1'; @@ -535,7 +550,7 @@ dut_bytes <= b"00"; dut_start <= '0'; dut_end <= '0'; - dut_di_ack <= '0'; + dut_di_wr <= '0'; wait until pclk'event and pclk = '1'; dut_ce <= '1'; dut_start <= '1'; @@ -543,11 +558,15 @@ dut_bytes <= b"00"; wait until pclk'event and pclk = '1'; dut_start <= '0'; - wait until dut_di_req = '1'; - dut_di_ack <= '1'; + dut_di_wr <= '1'; + if dut_di_req = '0' then + wait until dut_di_req = '1'; + end if; + dut_di_wr <= '1'; dut_end <= '1'; wait until pclk'event and pclk = '1'; dut_end <= '0'; + dut_di_wr <= '0'; if dut_error /= '1' and dut_do_valid /= '1' then while dut_error /= '1' and dut_do_valid /= '1' loop wait until pclk'event and pclk = '1'; @@ -577,16 +596,18 @@ dut_bytes <= b"00"; dut_start <= '0'; dut_end <= '0'; - dut_di_ack <= '0'; + dut_di_wr <= '0'; wait until pclk'event and pclk = '1'; dut_ce <= '1'; dut_start <= '1'; dut_di <= x"00000000"; dut_bytes <= b"00"; - dut_di_ack <= '1'; wait until pclk'event and pclk = '1'; dut_start <= '0'; - wait until dut_di_req = '1'; + dut_di_wr <= '1'; + if dut_di_req = '0' then + wait until dut_di_req = '1'; + end if; wait until pclk'event and pclk = '1'; wait until pclk'event and pclk = '1'; wait until pclk'event and pclk = '1'; @@ -604,6 +625,7 @@ dut_bytes <= b"11"; wait until pclk'event and pclk = '1'; dut_end <= '0'; + dut_di_wr <= '0'; if dut_error /= '1' and dut_do_valid /= '1' then while dut_error /= '1' and dut_do_valid /= '1' loop wait until pclk'event and pclk = '1'; @@ -633,16 +655,18 @@ dut_bytes <= b"00"; dut_start <= '0'; dut_end <= '0'; - dut_di_ack <= '0'; + dut_di_wr <= '0'; wait until pclk'event and pclk = '1'; dut_ce <= '1'; dut_start <= '1'; dut_di <= x"00000000"; dut_bytes <= b"00"; - dut_di_ack <= '1'; wait until pclk'event and pclk = '1'; dut_start <= '0'; - wait until dut_di_req = '1'; + dut_di_wr <= '1'; + if dut_di_req = '0' then + wait until dut_di_req = '1'; + end if; wait until pclk'event and pclk = '1'; wait until pclk'event and pclk = '1'; wait until pclk'event and pclk = '1'; @@ -659,6 +683,7 @@ dut_end <= '1'; wait until pclk'event and pclk = '1'; dut_end <= '0'; + dut_di_wr <= '0'; if dut_error /= '1' and dut_do_valid /= '1' then while dut_error /= '1' and dut_do_valid /= '1' loop wait until pclk'event and pclk = '1'; @@ -688,16 +713,18 @@ dut_bytes <= b"00"; dut_start <= '0'; dut_end <= '0'; - dut_di_ack <= '0'; + dut_di_wr <= '0'; wait until pclk'event and pclk = '1'; dut_ce <= '1'; dut_start <= '1'; dut_di <= x"00000000"; dut_bytes <= b"00"; - dut_di_ack <= '1'; wait until pclk'event and pclk = '1'; dut_start <= '0'; - wait until dut_di_req = '1'; + dut_di_wr <= '1'; + if dut_di_req = '0' then + wait until dut_di_req = '1'; + end if; wait until pclk'event and pclk = '1'; wait until pclk'event and pclk = '1'; wait until pclk'event and pclk = '1'; @@ -716,6 +743,7 @@ dut_bytes <= b"01"; wait until pclk'event and pclk = '1'; dut_end <= '0'; + dut_di_wr <= '0'; if dut_error /= '1' and dut_do_valid /= '1' then while dut_error /= '1' and dut_do_valid /= '1' loop wait until pclk'event and pclk = '1'; @@ -745,16 +773,18 @@ dut_bytes <= b"00"; dut_start <= '0'; dut_end <= '0'; - dut_di_ack <= '0'; + dut_di_wr <= '0'; wait until pclk'event and pclk = '1'; dut_ce <= '1'; dut_start <= '1'; dut_di <= x"00000000"; dut_bytes <= b"00"; - dut_di_ack <= '1'; wait until pclk'event and pclk = '1'; dut_start <= '0'; - wait until dut_di_req = '1'; + dut_di_wr <= '1'; + if dut_di_req = '0' then + wait until dut_di_req = '1'; + end if; wait until pclk'event and pclk = '1'; wait until pclk'event and pclk = '1'; wait until pclk'event and pclk = '1'; @@ -773,6 +803,7 @@ dut_end <= '1'; wait until pclk'event and pclk = '1'; dut_end <= '0'; + dut_di_wr <= '0'; if dut_error /= '1' and dut_do_valid /= '1' then while dut_error /= '1' and dut_do_valid /= '1' loop wait until pclk'event and pclk = '1'; @@ -802,13 +833,12 @@ dut_bytes <= b"00"; dut_start <= '0'; dut_end <= '0'; - dut_di_ack <= '0'; + dut_di_wr <= '0'; wait until pclk'event and pclk = '1'; dut_ce <= '1'; dut_start <= '1'; wait until pclk'event and pclk = '1'; dut_start <= '0'; - dut_di_ack <= '1'; dut_bytes <= b"00"; dut_di <= x"00000000"; count_words := 0; @@ -817,6 +847,8 @@ blocks <= count_blocks; loop wait until dut_di_req = '1'; + wait until pclk'event and pclk = '1'; + dut_di_wr <= '1'; loop wait until pclk'event and pclk = '1'; count_words := count_words + 1; @@ -823,6 +855,7 @@ words <= count_words; exit when words = 15; end loop; + dut_di_wr <= '0'; count_words := 0; words <= count_words; count_blocks := count_blocks + 1; @@ -832,6 +865,8 @@ count_words := 0; words <= count_words; wait until dut_di_req = '1'; + wait until pclk'event and pclk = '1'; + dut_di_wr <= '1'; loop wait until pclk'event and pclk = '1'; count_words := count_words + 1; @@ -841,6 +876,7 @@ dut_end <= '1'; wait until pclk'event and pclk = '1'; dut_end <= '0'; + dut_di_wr <= '0'; if dut_error /= '1' and dut_do_valid /= '1' then while dut_error /= '1' and dut_do_valid /= '1' loop wait until pclk'event and pclk = '1'; @@ -870,13 +906,12 @@ dut_bytes <= b"00"; dut_start <= '0'; dut_end <= '0'; - dut_di_ack <= '0'; + dut_di_wr <= '0'; wait until pclk'event and pclk = '1'; dut_ce <= '1'; dut_start <= '1'; wait until pclk'event and pclk = '1'; dut_start <= '0'; - dut_di_ack <= '1'; dut_bytes <= b"00"; dut_di <= x"41414141"; count_words := 0; @@ -885,6 +920,8 @@ blocks <= count_blocks; loop wait until dut_di_req = '1'; + wait until pclk'event and pclk = '1'; + dut_di_wr <= '1'; loop wait until pclk'event and pclk = '1'; count_words := count_words + 1; @@ -891,6 +928,7 @@ words <= count_words; exit when words = 15; end loop; + dut_di_wr <= '0'; count_words := 0; words <= count_words; count_blocks := count_blocks + 1; @@ -900,6 +938,8 @@ count_words := 0; words <= count_words; wait until dut_di_req = '1'; + wait until pclk'event and pclk = '1'; + dut_di_wr <= '1'; loop wait until pclk'event and pclk = '1'; count_words := count_words + 1; @@ -909,6 +949,7 @@ dut_end <= '1'; wait until pclk'event and pclk = '1'; dut_end <= '0'; + dut_di_wr <= '0'; if dut_error /= '1' and dut_do_valid /= '1' then while dut_error /= '1' and dut_do_valid /= '1' loop wait until pclk'event and pclk = '1'; @@ -938,13 +979,12 @@ dut_bytes <= b"00"; dut_start <= '0'; dut_end <= '0'; - dut_di_ack <= '0'; + dut_di_wr <= '0'; wait until pclk'event and pclk = '1'; dut_ce <= '1'; dut_start <= '1'; wait until pclk'event and pclk = '1'; dut_start <= '0'; - dut_di_ack <= '1'; dut_bytes <= b"00"; dut_di <= x"55555555"; count_words := 0; @@ -953,6 +993,8 @@ blocks <= count_blocks; loop wait until dut_di_req = '1'; + wait until pclk'event and pclk = '1'; + dut_di_wr <= '1'; loop wait until pclk'event and pclk = '1'; count_words := count_words + 1; @@ -959,6 +1001,7 @@ words <= count_words; exit when words = 15; end loop; + dut_di_wr <= '0'; count_words := 0; words <= count_words; count_blocks := count_blocks + 1; @@ -968,6 +1011,8 @@ count_words := 0; words <= count_words; wait until dut_di_req = '1'; + wait until pclk'event and pclk = '1'; + dut_di_wr <= '1'; loop wait until pclk'event and pclk = '1'; count_words := count_words + 1; @@ -979,6 +1024,7 @@ dut_end <= '1'; wait until pclk'event and pclk = '1'; dut_end <= '0'; + dut_di_wr <= '0'; if dut_error /= '1' and dut_do_valid /= '1' then while dut_error /= '1' and dut_do_valid /= '1' loop wait until pclk'event and pclk = '1'; @@ -1008,13 +1054,12 @@ dut_bytes <= b"00"; dut_start <= '0'; dut_end <= '0'; - dut_di_ack <= '0'; + dut_di_wr <= '0'; wait until pclk'event and pclk = '1'; dut_ce <= '1'; dut_start <= '1'; wait until pclk'event and pclk = '1'; dut_start <= '0'; - dut_di_ack <= '1'; dut_bytes <= b"00"; dut_di <= x"00000000"; count_words := 0; @@ -1023,6 +1068,8 @@ blocks <= count_blocks; loop wait until dut_di_req = '1'; + wait until pclk'event and pclk = '1'; + dut_di_wr <= '1'; loop wait until pclk'event and pclk = '1'; count_words := count_words + 1; @@ -1029,6 +1076,7 @@ words <= count_words; exit when words = 15; end loop; + dut_di_wr <= '0'; count_words := 0; words <= count_words; count_blocks := count_blocks + 1; @@ -1038,6 +1086,8 @@ count_words := 0; words <= count_words; wait until dut_di_req = '1'; + wait until pclk'event and pclk = '1'; + dut_di_wr <= '1'; loop wait until pclk'event and pclk = '1'; count_words := count_words + 1; @@ -1047,6 +1097,7 @@ dut_end <= '1'; wait until pclk'event and pclk = '1'; dut_end <= '0'; + dut_di_wr <= '0'; if dut_error /= '1' and dut_do_valid /= '1' then while dut_error /= '1' and dut_do_valid /= '1' loop wait until pclk'event and pclk = '1'; Index: syn/sha256/sha256_control.vhd =================================================================== --- syn/sha256/sha256_control.vhd (revision 8) +++ syn/sha256/sha256_control.vhd (revision 9) @@ -43,7 +43,7 @@ -- The engine is internally implemented as a 256-bit machine, with all combinational operations performed as a single-cycle operation on each -- 64 steps of the hash algorithm. Wide transfers of 256-bit data are also performed as single-cycle operations. -- --- The data input accepts 16 consecutive 32bit words for a total of 64 bytes per block, one word per clock cycle. The input signal 'ack_i' can be +-- The data input accepts 16 consecutive 32bit words for a total of 64 bytes per block, one word per clock cycle. The input signal 'wr_i' can be -- used as a flow control input to hold the processor to wait for slower data. -- -- A hash computation starts with a 'start_i' pulse that resets the processor. A pulse of the 'end_i' signal marks the last input data word. The @@ -72,7 +72,7 @@ -- __ _ _ _ _____________________________________________________________________________________________________ -- di_req_o __ _ _ _\_____/ \_______________... -- 'di_req_o' asserted during data input -- ___________________________________________ _________________________________________________________ --- ack_i __________/____/ \_____/ \_____________... -- 'ack_i' can hold the core for slow data +-- wr_i __________/____/ \_____/ \_____________... -- 'wr_i' can hold the core for slow data -- __________ _________ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ ______ ______________... -- di_i __________\___\_W0__\__W1_\__W2_\__W3_\__W4_\__W5_\\\\\\\__W6_\__W7_\__W8_\__W9_\_W10_\_W11_\_W12_\_W13_\_W14_\_W15__\______X_______... -- user words on 'di_i' are latched on 'clk_i' rising edge -- ____________________ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ _____________________... @@ -100,7 +100,7 @@ -- _____________________________________________________________________________________________________ -- di_req_o ____________________/ \___... -- 'di_req_o' asserted during data input -- ___________________________________________________ _________________________________________________________ --- ack_i ________/__________/ \_____/ \_... -- 'ack_i' can hold the core for slow data +-- wr_i ________/__________/ \_____/ \_... -- 'wr_i' can hold the core for slow data -- _________________ _ ______ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ _____ _____ ____... -- di_i _________________\\\___W0_\__W1_\__W2_\__W3_\__W4_\__W5_\\\\\\\\_W6_\__W7_\__W8_\__W9_\_W10_\_W11_\_W12_\_W13_\_W14_\_W15_\\_X_... -- user words on 'di_i' are latched on 'clk_i' rising edge -- @@ -118,7 +118,7 @@ -- _______ _ _ ___________________________________________________________________________________________________________ -- di_req_o ________/ \___... -- 'di_req_o' asserted during data input -- __________________________________________________ _____________________________________________ --- ack_i ________________ _ _ ______/ \_____/ \_... -- 'ack_i' valid on rising edge of 'clk_i' +-- wr_i ________________ _ _ ______/ \_____/ \_... -- 'wr_i' valid on rising edge of 'clk_i' -- ________________ _ _ ___________ _____ _____ _____ _____ _____ _____ _____ ___________ _____ _____ _____ _____ _____ _____ _____ ____... -- di_i ________________ _ _ ______\_W0_\__W1_\__W2_\__W3_\__W4_\__W5_\__W6_\__W7_\\\\\\\__W8_\__W9_\_W10_\_W11_\_W12_\_W13_\_W14_\_W15_\\_Z_... -- user words on 'di_i' are latched on 'clk_i' rising edge -- @@ -141,7 +141,7 @@ -- ___________________________________ __________ -- di_req_o ________/ \__________ _ _ ___________________ _ _ ________________________________/ ... -- 'di_req_o' asserted during data input -- ______________________________________ _________ --- ack_i _________/ \\\______ _ _ ___________________ _ _ _________________________________/ ... -- 'ack_i' can hold the core for slow data +-- wr_i _________/ \\\______ _ _ ___________________ _ _ _________________________________/ ... -- 'wr_i' can hold the core for slow data -- ______________ _____ _____ _____ _____ _____ __________ _ _ ___________________ _ _ ______________________________________ ____... -- di_i _________\_W0_\__W1_\__W2_\__W3_\__W4_\__W5_\__________ _ _ ___________________ _ _ _________________________________\_W0_\__W1... -- words after the end_i assertion are ignored -- __ _____ _____ _____ _____ _____ _____ _____ _____ ____ _ ____ _____ _____ ____ _ _ ______________________________________ ____ @@ -186,7 +186,7 @@ -- _________________ __________ -- di_req_o \__________ _ _ ___________________ _ _ _____________ _ _ __________________________/ ... -- 'di_req_o' asserted on rising edge of 'clk_i' -- ____________________ _________ --- ack_i \\\_______ _ _ ___________________ _ _ _____________ _ _ ___________________________/ ... -- 'ack_i' valid on rising edge of 'clk_i' +-- wr_i \\\_______ _ _ ___________________ _ _ _____________ _ _ ___________________________/ ... -- 'wr_i' valid on rising edge of 'clk_i' -- _____ _____ _____ __________ _ _ ___________________ _ _ _____________ _ _ ________________________________ ____... -- di_i _W13_\_W14_\_W15_\__________ _ _ ___________________ _ _ _____________ _ _ ___________________________\_W0_\__W1... -- words after the end_i assertion are ignored -- _____ _____ _____ _____ ____ _ ____ _____ _____ ____ _ _ ________ ____ _ ____ _____ _______________________ ____ @@ -198,29 +198,29 @@ -- -- ------------------------------ COPYRIGHT NOTICE ----------------------------------------------------------------------- --- --- This file is part of the SHA256 HASH CORE project http://opencores.org/project,sha256_hash_core --- --- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gridvortex.com, jonnydoin@gmail.com --- --- Copyright (C) 2016 Jonny Doin --- ----------------------------- --- --- This source file may be used and distributed without restriction provided that this copyright statement is not --- removed from the file and that any derivative work contains the original copyright notice and the associated --- disclaimer. --- --- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser --- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or --- (at your option) any later version. --- --- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied --- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more --- details. --- --- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download --- it from http://www.gnu.org/licenses/lgpl.txt --- +-- +-- This file is part of the SHA256 HASH CORE project http://opencores.org/project,sha256_hash_core +-- +-- Author(s): Jonny Doin, jdoin@opencores.org, jonnydoin@gridvortex.com, jonnydoin@gmail.com +-- +-- Copyright (C) 2016 Jonny Doin +-- ----------------------------- +-- +-- This source file may be used and distributed without restriction provided that this copyright statement is not +-- removed from the file and that any derivative work contains the original copyright notice and the associated +-- disclaimer. +-- +-- This source file is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser +-- General Public License as published by the Free Software Foundation; either version 2.1 of the License, or +-- (at your option) any later version. +-- +-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied +-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more +-- details. +-- +-- You should have received a copy of the GNU Lesser General Public License along with this source; if not, download +-- it from http://www.gnu.org/licenses/lgpl.txt +-- ------------------------------ REVISION HISTORY ----------------------------------------------------------------------- -- -- 2016/05/22 v0.01.0010 [JD] started development. design of blocks and port interfaces. @@ -233,6 +233,7 @@ -- 2016/06/11 v0.01.0110 [JD] optimized controller states, reduced 2 clocks per block. -- 2016/06/18 v0.01.0120 [JD] implemented error detection on 'bytes_i' input. -- 2016/07/06 v0.01.0210 [JD] optimized suspend logic on 'sch_ld' to supress possible glitch in 'pad_one_next'. +-- 2016/09/25 v0.01.0220 [JD] changed 'ack_i' name to 'wr_i', and changed semantics to 'data write'. -- ----------------------------------------------------------------------------------------------------------------------- -- TODO @@ -251,7 +252,7 @@ ce_i : in std_logic := 'U'; -- core clock enable start_i : in std_logic := 'U'; -- reset the processor and start a new hash end_i : in std_logic := 'U'; -- marks end of last block data input - ack_i : in std_logic := 'U'; -- input word hold control + wr_i : in std_logic := 'U'; -- input word write/hold control bytes_i : in std_logic_vector (1 downto 0) := (others => 'U'); -- valid bytes in input word error_i : in std_logic := 'U'; -- datapath error input from other modules -- output control signals @@ -335,8 +336,10 @@ signal bytes_ena : std_logic_vector (3 downto 0); -- byte lane selectors for padding logic block signal one_insert : std_logic; -- insert leading one in the padding signal di_req : std_logic; -- data request + signal di_wr_window : std_logic; -- valid data write window signal data_valid : std_logic; -- operation finished. output data is valid signal core_error : std_logic; -- operation aborted. output data is not valid + signal data_input_error : std_logic; -- internal error signal for data write signal out_error : std_logic; -- operation aborted. output data is not valid begin @@ -352,6 +355,7 @@ -- all registered values are reset on master clear hash_control_st_reg <= st_reset; elsif out_error = '1' then + -- error latch: lock on the error state hash_control_st_reg <= st_error; elsif ce_i = '1' then -- all registered values are held on master clock enable @@ -439,6 +443,7 @@ -- handshaking sha_init <= '0'; core_error <= '0'; + di_wr_window <= '0'; words_sel <= b"00"; data_valid <= '0'; di_req <= '0'; -- data request only during data input @@ -464,6 +469,7 @@ core_ld <= '1'; -- load initial value into core registers core_ce <= '1'; -- latch initial value into core registers st_cnt_clr <= '1'; -- reset state counter + di_wr_window <= '1'; -- enable data write window -- next state hash_control_st_next <= st_sha_data_input; @@ -470,6 +476,7 @@ when st_sha_data_input => -- message data words are clocked into the processor -- moore outputs di_req <= '1'; -- request message data + di_wr_window <= '1'; -- enable data write window sch_ce <= wait_run_ce; -- hold the message scheduler with data hold st_cnt_ce <= wait_run_ce; -- hold state count with data hold core_ce <= wait_run_ce; -- hold processing clock with data hold @@ -611,8 +618,8 @@ msg_bit_cnt_next <= msg_bit_cnt_reg + bits_to_add; end process msg_bit_cnt_next_combi_proc; - -- data input wait/run: insert wait states during data input for 'ack_i' = '0' - wait_run_proc: wait_run_ce <= '1' when di_req = '1' and ack_i = '1' else '0'; + -- data input wait/run: insert wait states during data input for 'wr_i' = '0' + wait_run_proc: wait_run_ce <= '1' when di_req = '1' and wr_i = '1' else '0'; -- padding one-insertion control one_insert_proc: one_insert <= '1' when pad_one_reg = '1' else '0'; @@ -624,10 +631,13 @@ st_cnt_next_proc: st_cnt_next <= st_cnt_reg + 1; -- bytes_i error logic - bytes_error_proc: bytes_error_next <= '1' when bytes_i /= b"00" and end_i /= '1' and di_req = '1' and ack_i = '1' else bytes_error_reg; + bytes_error_proc: bytes_error_next <= '1' when bytes_i /= b"00" and end_i /= '1' and di_req = '1' and wr_i = '1' else bytes_error_reg; + -- data input error logic + data_input_error_proc: data_input_error <= '1' when wr_i = '1' and di_wr_window /= '1' else '0'; + -- error detection logic - out_error_combi_proc: out_error <= '1' when error_i = '1' or core_error = '1' or bytes_error_reg = '1' else '0'; + out_error_combi_proc: out_error <= '1' when error_i = '1' or core_error = '1' or bytes_error_reg = '1' or data_input_error = '1' else '0'; --============================================================================================= -- OUTPUT LOGIC PROCESSES

/syn/sha256/sha256.wcfg

/syn/sha256/iseconfig/sha256.projectmgr

/syn/sha256/iseconfig/gv_sha256.xreport