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/trunk/dsm2/dac_dsm2v.vhd
0,0 → 1,69
------------------------------------------------------------------------------- |
-- Title : DAC_DSM2 - sigma-delta DAC converter with double loop |
-- Project : |
------------------------------------------------------------------------------- |
-- File : dac_dsm2.vhd |
-- Author : Wojciech M. Zabolotny ( wzab[at]ise.pw.edu.pl ) |
-- Company : |
-- Created : 2009-04-28 |
-- Last update: 2009-04-29 |
-- Platform : |
-- Standard : VHDL'93c |
------------------------------------------------------------------------------- |
-- Description: Implementation with use of variables inside of process |
------------------------------------------------------------------------------- |
-- Copyright (c) 2009 - THIS IS PUBLIC DOMAIN CODE!!! |
------------------------------------------------------------------------------- |
-- Revisions : |
-- Date Version Author Description |
-- 2009-04-28 1.0 wzab Created |
------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
entity dac_dsm2v is |
|
generic ( |
nbits : integer := 16); |
|
port ( |
din : in signed((nbits-1) downto 0); |
dout : out std_logic; |
clk : in std_logic; |
n_rst : in std_logic); |
|
end dac_dsm2v; |
|
architecture beh1 of dac_dsm2v is |
|
signal del1, del2, d_q : signed(nbits+2 downto 0) := (others => '0'); |
constant c1 : signed(nbits+2 downto 0) := to_signed(1, nbits+3); |
constant c_1 : signed(nbits+2 downto 0) := to_signed(-1, nbits+3); |
begin -- beh1 |
|
process (clk, n_rst) |
variable v1, v2 : signed(nbits+2 downto 0) := (others => '0'); |
begin -- process |
if n_rst = '0' then -- asynchronous reset (active low) |
del1 <= (others => '0'); |
del2 <= (others => '0'); |
dout <= '0'; |
elsif clk'event and clk = '1' then -- rising clock edge |
v1 := din - d_q + del1; |
v2 := v1 - d_q + del2; |
if v2 > 0 then |
d_q <= shift_left(c1, nbits); |
dout <= '1'; |
else |
d_q <= shift_left(c_1, nbits); |
dout <= '0'; |
end if; |
del1 <= v1; |
del2 <= v2; |
end if; |
end process; |
|
|
end beh1; |
/trunk/dsm2/dac_dsm2.vhd
0,0 → 1,66
------------------------------------------------------------------------------- |
-- Title : DAC_DSM2 - sigma-delta DAC converter with double loop |
-- Project : |
------------------------------------------------------------------------------- |
-- File : dac_dsm2.vhd |
-- Author : Wojciech M. Zabolotny ( wzab[at]ise.pw.edu.pl ) |
-- Company : |
-- Created : 2009-04-28 |
-- Last update: 2009-04-29 |
-- Platform : |
-- Standard : VHDL'93c |
------------------------------------------------------------------------------- |
-- Description: Implementation without variables |
------------------------------------------------------------------------------- |
-- Copyright (c) 2009 - THIS IS PUBLIC DOMAIN CODE!!! |
------------------------------------------------------------------------------- |
-- Revisions : |
-- Date Version Author Description |
-- 2009-04-28 1.0 wzab Created |
------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
entity dac_dsm2 is |
|
generic ( |
nbits : integer := 16); |
|
port ( |
din : in signed((nbits-1) downto 0); |
dout : out std_logic; |
clk : in std_logic; |
n_rst : in std_logic); |
|
end dac_dsm2; |
|
architecture beh1 of dac_dsm2 is |
|
signal del1, del2, d_q : signed(nbits+2 downto 0) := (others => '0'); |
constant c1 : signed(nbits+2 downto 0) := to_signed(1, nbits+3); |
constant c_1 : signed(nbits+2 downto 0) := to_signed(-1, nbits+3); |
begin -- beh1 |
|
process (clk, n_rst) |
begin -- process |
if n_rst = '0' then -- asynchronous reset (active low) |
del1 <= (others => '0'); |
del2 <= (others => '0'); |
dout <= '0'; |
elsif clk'event and clk = '1' then -- rising clock edge |
del1 <= din - d_q + del1; |
del2 <= din - d_q + del1 - d_q + del2; |
if din - d_q + del1 - d_q + del2 > 0 then |
d_q <= shift_left(c1, nbits); |
dout <= '1'; |
else |
d_q <= shift_left(c_1, nbits); |
dout <= '0'; |
end if; |
end if; |
end process; |
|
|
end beh1; |
/trunk/dsm2/dac_tb.vhd
0,0 → 1,136
------------------------------------------------------------------------------- |
-- Title : Testbench for design "dac_dsm2" |
-- Project : |
------------------------------------------------------------------------------- |
-- File : dac_dsm2_tb.vhd |
-- Author : Wojciech M. Zabolotny ( wzab[at]ise.pw.edu.pl ) |
-- Company : |
-- Created : 2009-04-28 |
-- Last update: 2012-10-16 |
-- Platform : |
-- Standard : VHDL'93c |
------------------------------------------------------------------------------- |
-- Description: Testbench for S-D DAC converters |
------------------------------------------------------------------------------- |
-- Copyright (c) 2009 - THIS IS PUBLIC DOMAIN CODE!!! |
------------------------------------------------------------------------------- |
-- Revisions : |
-- Date Version Author Description |
-- 2009-04-28 1.0 wzab Created |
------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
use ieee.math_real.all; |
use std.textio.all; |
|
------------------------------------------------------------------------------- |
|
entity dac_tb is |
|
end dac_tb; |
|
------------------------------------------------------------------------------- |
|
architecture beh1 of dac_tb is |
|
-- Configuration of the testbench |
-- Clock period [ns] |
constant TCLK : time := 10 ns; |
constant OSR : real := 256.0; -- Oversampling ratio: |
|
constant FREQ1 : real := 0.35; -- Frequency of the first sinusoid (relative to the sampling frequency) |
constant AMP1 : real := 0.2; -- Amplitude of the first sinusoid |
constant PHASE1 : real := 0.35; -- Phase of the first sinusoid |
constant FREQ2 : real := 0.3; -- Frequency of the second sinusoid (relative to the sampling frequency) |
constant AMP2 : real := 0.4; -- Amplitude of the second sinusoid |
constant PHASE2 : real := 0.35; -- Phase of the second sinusoid |
constant FREQ3 : real := 0.25; -- Frequency of the third sinusoid (relative to the sampling frequency) |
constant AMP3 : real := 0.3; -- Amplitude of the third sinusoid |
constant PHASE3 : real := 0.35; -- Phase of the third sinusoid |
constant TSTEP : real := 3.1415926 / OSR; -- Phase/time step of the sinusoid generation (considering the OSR) |
|
file OUTFILE : text is out "dac_tb.dat"; |
|
component dac_dsm2_top |
generic ( |
nbits : integer); |
port ( |
din : in signed((nbits-1) downto 0); |
dout : out std_logic; |
clk : in std_logic; |
n_rst : in std_logic); |
end component; |
|
-- component generics |
constant nbits : integer := 16; |
|
-- component ports |
signal din : signed((nbits-1) downto 0) := (others => '0'); |
signal dout : std_logic := '0'; |
signal n_rst : std_logic := '0'; |
|
-- input signal |
signal s_inp : real := 0.0; |
signal s_time : real := 0.0; |
-- clock |
signal Clk : std_logic := '1'; |
|
begin -- beh1 |
|
-- component instantiation |
DUT1 : dac_dsm2_top |
generic map ( |
nbits => nbits) |
port map ( |
din => din, |
dout => dout, |
clk => clk, |
n_rst => n_rst); |
|
-- clock generation |
Clk <= not Clk after TCLK/2.0; |
|
-- Generation of input signal and simulation of DACs |
din <= to_signed(integer(s_inp), nbits); |
process (clk, n_rst) |
variable s : line; |
variable c : character := ' '; |
variable c1 : character := '1'; |
variable c0 : character := '0'; |
begin -- process |
if n_rst = '0' then -- asynchronous reset (active low) |
s_time <= 0.0; |
elsif clk'event and clk = '1' then -- rising clock edge |
s_time <= s_time+TSTEP; |
s_inp <= (2.0**(nbits-1))*( |
AMP1 * sin(s_time*FREQ1+PHASE1) + |
AMP2 * sin(s_time*FREQ2+PHASE2) + |
AMP3 * sin(s_time*FREQ3+PHASE3) |
); |
-- Write results to file |
write(s, s_inp); |
write(s, c); |
|
if dout = '1' then |
write(s, c1); |
else |
write(s, c0); |
end if; |
writeline(OUTFILE, s); |
end if; |
end process; |
|
-- waveform generation |
WaveGen_Proc : process |
begin |
-- insert signal assignments here |
wait until Clk = '1'; |
wait for 25 ns; |
n_rst <= '1'; |
end process WaveGen_Proc; |
|
end beh1; |
|
|
/trunk/dsm2/makefile
0,0 → 1,22
VHDLS = \ |
dac_dsm2.vhd \ |
dac_dsm2v.vhd \ |
dac_dsm2_top.vhd \ |
dac_tb.vhd \ |
|
|
STD=standard |
#STD=synopsys |
show_spectra: dac_tb.dat |
python show_dac.py |
show_ghw: dac_tb dac_tb.ghw |
gtkwave dac_tb.ghw wzrmb.sav |
dac_tb: ${VHDLS} |
ghdl -a --std=93c --ieee=${STD} ${VHDLS} |
ghdl -e --std=93c -fexplicit --ieee=${STD} dac_tb |
dac_tb.dat: dac_tb |
./dac_tb --wave=dac_tb.ghw --stop-time=2000000ns |
dac_tb.ghw: dac_tb |
./dac_tb --wave=dac_tb.ghw --stop-time=2000000ns |
clean: |
rm *.o *.vcd *.ghw *.dat *.cf dac_tb |
/trunk/dsm2/dac_dsm2_top.vhd
0,0 → 1,58
------------------------------------------------------------------------------- |
-- Title : DAC_DSM2 - sigma-delta DAC converter with double loop |
-- Project : |
------------------------------------------------------------------------------- |
-- File : dac_dsm2.vhd |
-- Author : Wojciech M. Zabolotny ( wzab[at]ise.pw.edu.pl ) |
-- Company : |
-- Created : 2009-04-28 |
-- Last update: 2012-10-16 |
-- Platform : |
-- Standard : VHDL'93c |
------------------------------------------------------------------------------- |
-- Description: Top entity |
------------------------------------------------------------------------------- |
-- Copyright (c) 2009 - THIS IS PUBLIC DOMAIN CODE!!! |
------------------------------------------------------------------------------- |
-- Revisions : |
-- Date Version Author Description |
-- 2009-04-28 1.0 wzab Created |
------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
entity dac_dsm2_top is |
generic ( |
nbits : integer); |
port ( |
din : in signed(15 downto 0); |
dout : out std_logic; |
clk : in std_logic; |
n_rst : in std_logic); |
|
end dac_dsm2_top; |
|
architecture beh1 of dac_dsm2_top is |
|
component dac_dsm2 |
generic ( |
nbits : integer); |
port ( |
din : in signed((nbits-1) downto 0); |
dout : out std_logic; |
clk : in std_logic; |
n_rst : in std_logic); |
end component; |
|
begin |
dac_dsm2_1 : dac_dsm2 |
generic map ( |
nbits => nbits) |
port map ( |
din => din, |
dout => dout, |
clk => clk, |
n_rst => n_rst); |
end beh1; |
/trunk/dsm2/show_dac.py
0,0 → 1,14
import pylab |
#w=load("dac_tb.dat") |
import numpy |
w=numpy.loadtxt("dac_tb.dat") |
t1=[i[1] for i in w]; t1=t1-pylab.mean(t1) |
f1=20.0*pylab.log(0.0001+abs(pylab.fft(t1))) |
pylab.plot(f1) |
pylab.title("Whole spectra of output signal") |
pylab.grid() |
pylab.show() |
pylab.plot(f1[0:1000]) |
pylab.title("First 1000 samples of spectra") |
pylab.grid() |
pylab.show() |
/trunk/dsm3/dac_dsm3_top.vhd
0,0 → 1,97
------------------------------------------------------------------------------- |
-- Title : DAC_DSM2 - sigma-delta DAC converter with double loop |
-- Project : |
------------------------------------------------------------------------------- |
-- File : dac_dsm2.vhd |
-- Author : Wojciech M. Zabolotny ( wzab[at]ise.pw.edu.pl ) |
-- Company : |
-- Created : 2009-04-28 |
-- Last update: 2012-10-16 |
-- Platform : |
-- Standard : VHDL'93c |
------------------------------------------------------------------------------- |
-- Description: Top entity - contains DAC and output circuit |
-- generating the 3-bit sequences |
------------------------------------------------------------------------------- |
-- Copyright (c) 2009 - THIS IS PUBLIC DOMAIN CODE!!! |
------------------------------------------------------------------------------- |
-- Revisions : |
-- Date Version Author Description |
-- 2009-04-28 1.0 wzab Created |
------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
entity dac_dsm3_top is |
generic ( |
nbits : integer); |
port ( |
din : in signed(15 downto 0); |
dout : out std_logic; |
clk : in std_logic; |
n_rst : in std_logic); |
|
end dac_dsm3_top; |
|
architecture beh1 of dac_dsm3_top is |
|
component dac_dsm3 |
generic ( |
nbits : integer); |
port ( |
din : in signed((nbits-1) downto 0); |
dout : out std_logic; |
clk : in std_logic; |
clk_ena : in std_logic; |
n_rst : in std_logic); |
end component; |
|
signal clk_cnt : integer range 0 to 2 := 0; |
signal clk_ena : std_logic := '0'; |
signal dac_dout : std_logic := '0'; |
|
begin |
-- The clock cycle counter |
clken1 : process (clk, n_rst) |
begin -- process |
if n_rst = '0' then -- asynchronous reset (active low) |
clk_cnt <= 0; |
elsif clk'event and clk = '1' then -- rising clock edge |
-- Update the cycle counter |
if clk_cnt < 2 then |
clk_cnt <= clk_cnt + 1; |
else |
clk_cnt <= 0; |
end if; |
-- Generate the clk_ena only in the first cycle |
if clk_cnt = 2 then |
clk_ena <= '1'; |
else |
clk_ena <= '0'; |
end if; |
-- Generate the narrow (if dac_dout='0') or wide (if dac_output='1') |
-- output pulse |
if clk_cnt = 0 then |
dout <= '1'; -- always the rising slope after the first |
-- clock cycle |
elsif (clk_cnt = 1) and (dac_dout = '0') then |
dout <= '0'; -- short dout pulse when dac_dout = '0' |
elsif clk_cnt = 2 then |
dout <= '0'; -- always the falling slope after the |
-- third cycle |
end if; |
end if; |
end process clken1; |
|
dac_dsm3_1 : dac_dsm3 |
generic map ( |
nbits => 16) |
port map ( |
din => din, |
dout => dout, |
clk => clk, |
clk_ena => clk_ena, |
n_rst => n_rst); |
end beh1; |
/trunk/dsm3/dac_dsm3v.vhd
0,0 → 1,73
------------------------------------------------------------------------------- |
-- Title : DAC_DSM3 - sigma-delta DAC converter with double loop |
-- Project : |
------------------------------------------------------------------------------- |
-- File : dac_dsm2.vhd |
-- Author : Wojciech M. Zabolotny ( wzab[at]ise.pw.edu.pl ) |
-- Company : |
-- Created : 2009-04-28 |
-- Last update: 2012-10-16 |
-- Platform : |
-- Standard : VHDL'93c |
------------------------------------------------------------------------------- |
-- Description: Implementation with use of variables inside of process |
-- : and with one rising and falling slope for each output cycle |
------------------------------------------------------------------------------- |
-- Copyright (c) 2009 - THIS IS PUBLIC DOMAIN CODE!!! |
------------------------------------------------------------------------------- |
-- Revisions : |
-- Date Version Author Description |
-- 2009-04-28 1.0 wzab Created |
------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
entity dac_dsm3v is |
|
generic ( |
nbits : integer := 16); |
|
port ( |
din : in signed((nbits-1) downto 0); |
dout : out std_logic; |
clk : in std_logic; |
clk_ena : in std_logic; |
n_rst : in std_logic); |
|
end dac_dsm3v; |
|
architecture beh1 of dac_dsm3v is |
|
signal del1, del2, d_q : signed(nbits+2 downto 0) := (others => '0'); |
constant c1 : signed(nbits+2 downto 0) := to_signed(1, nbits+3); |
constant c_1 : signed(nbits+2 downto 0) := to_signed(-1, nbits+3); |
begin -- beh1 |
|
process (clk, n_rst) |
variable v1, v2 : signed(nbits+2 downto 0) := (others => '0'); |
begin -- process |
if n_rst = '0' then -- asynchronous reset (active low) |
del1 <= (others => '0'); |
del2 <= (others => '0'); |
dout <= '0'; |
elsif clk'event and clk = '1' then -- rising clock edge |
if clk_ena = '1' then |
v1 := din - d_q + del1; |
v2 := v1 - d_q + del2; |
if v2 > 0 then |
d_q <= shift_left(c1, nbits); |
dout <= '1'; |
else |
d_q <= shift_left(c_1, nbits); |
dout <= '0'; |
end if; |
del1 <= v1; |
del2 <= v2; |
end if; |
end if; |
end process; |
|
|
end beh1; |
/trunk/dsm3/dac_tb.vhd
0,0 → 1,136
------------------------------------------------------------------------------- |
-- Title : Testbench for design "dac_dsm2" |
-- Project : |
------------------------------------------------------------------------------- |
-- File : dac_dsm2_tb.vhd |
-- Author : Wojciech M. Zabolotny ( wzab[at]ise.pw.edu.pl ) |
-- Company : |
-- Created : 2009-04-28 |
-- Last update: 2012-10-16 |
-- Platform : |
-- Standard : VHDL'93c |
------------------------------------------------------------------------------- |
-- Description: Testbench for S-D DAC converters |
------------------------------------------------------------------------------- |
-- Copyright (c) 2009 - THIS IS PUBLIC DOMAIN CODE!!! |
------------------------------------------------------------------------------- |
-- Revisions : |
-- Date Version Author Description |
-- 2009-04-28 1.0 wzab Created |
------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
use ieee.math_real.all; |
use std.textio.all; |
|
------------------------------------------------------------------------------- |
|
entity dac_tb is |
|
end dac_tb; |
|
------------------------------------------------------------------------------- |
|
architecture beh1 of dac_tb is |
|
-- Configuration of the testbench |
-- Clock period [ns] |
constant TCLK : time := 10 ns; |
constant OSR : real := 256.0; -- Oversampling ratio: |
|
constant FREQ1 : real := 0.35; -- Frequency of the first sinusoid (relative to the sampling frequency) |
constant AMP1 : real := 0.2; -- Amplitude of the first sinusoid |
constant PHASE1 : real := 0.35; -- Phase of the first sinusoid |
constant FREQ2 : real := 0.3; -- Frequency of the second sinusoid (relative to the sampling frequency) |
constant AMP2 : real := 0.4; -- Amplitude of the second sinusoid |
constant PHASE2 : real := 0.35; -- Phase of the second sinusoid |
constant FREQ3 : real := 0.25; -- Frequency of the third sinusoid (relative to the sampling frequency) |
constant AMP3 : real := 0.3; -- Amplitude of the third sinusoid |
constant PHASE3 : real := 0.35; -- Phase of the third sinusoid |
constant TSTEP : real := 3.1415926 / OSR; -- Phase/time step of the sinusoid generation (considering the OSR) |
|
file OUTFILE : text is out "dac_tb.dat"; |
|
component dac_dsm3_top |
generic ( |
nbits : integer); |
port ( |
din : in signed((nbits-1) downto 0); |
dout : out std_logic; |
clk : in std_logic; |
n_rst : in std_logic); |
end component; |
|
-- component generics |
constant nbits : integer := 16; |
|
-- component ports |
signal din : signed((nbits-1) downto 0) := (others => '0'); |
signal dout : std_logic := '0'; |
signal n_rst : std_logic := '0'; |
|
-- input signal |
signal s_inp : real := 0.0; |
signal s_time : real := 0.0; |
-- clock |
signal Clk : std_logic := '1'; |
|
begin -- beh1 |
|
-- component instantiation |
DUT1 : dac_dsm3_top |
generic map ( |
nbits => nbits) |
port map ( |
din => din, |
dout => dout, |
clk => clk, |
n_rst => n_rst); |
|
-- clock generation |
Clk <= not Clk after TCLK/2.0; |
|
-- Generation of input signal and simulation of DACs |
din <= to_signed(integer(s_inp), nbits); |
process (clk, n_rst) |
variable s : line; |
variable c : character := ' '; |
variable c1 : character := '1'; |
variable c0 : character := '0'; |
begin -- process |
if n_rst = '0' then -- asynchronous reset (active low) |
s_time <= 0.0; |
elsif clk'event and clk = '1' then -- rising clock edge |
s_time <= s_time+TSTEP; |
s_inp <= (2.0**(nbits-1))*( |
AMP1 * sin(s_time*FREQ1+PHASE1) + |
AMP2 * sin(s_time*FREQ2+PHASE2) + |
AMP3 * sin(s_time*FREQ3+PHASE3) |
); |
-- Write results to file |
write(s, s_inp); |
write(s, c); |
|
if dout = '1' then |
write(s, c1); |
else |
write(s, c0); |
end if; |
writeline(OUTFILE, s); |
end if; |
end process; |
|
-- waveform generation |
WaveGen_Proc : process |
begin |
-- insert signal assignments here |
wait until Clk = '1'; |
wait for 25 ns; |
n_rst <= '1'; |
end process WaveGen_Proc; |
|
end beh1; |
|
|
/trunk/dsm3/dac_dsm3.vhd
0,0 → 1,69
------------------------------------------------------------------------------- |
-- Title : DAC_DSM2 - sigma-delta DAC converter with double loop |
-- Project : |
------------------------------------------------------------------------------- |
-- File : dac_dsm2.vhd |
-- Author : Wojciech M. Zabolotny ( wzab[at]ise.pw.edu.pl ) |
-- Company : |
-- Created : 2009-04-28 |
-- Last update: 2012-10-16 |
-- Platform : |
-- Standard : VHDL'93c |
------------------------------------------------------------------------------- |
-- Description: Implementation without variables |
------------------------------------------------------------------------------- |
-- Copyright (c) 2009 - THIS IS PUBLIC DOMAIN CODE!!! |
------------------------------------------------------------------------------- |
-- Revisions : |
-- Date Version Author Description |
-- 2009-04-28 1.0 wzab Created |
------------------------------------------------------------------------------- |
|
library ieee; |
use ieee.std_logic_1164.all; |
use ieee.numeric_std.all; |
|
entity dac_dsm3 is |
|
generic ( |
nbits : integer := 16); |
|
port ( |
din : in signed((nbits-1) downto 0); |
dout : out std_logic; |
clk : in std_logic; |
clk_ena : in std_logic; |
n_rst : in std_logic); |
|
end dac_dsm3; |
|
architecture beh1 of dac_dsm3 is |
|
signal del1, del2, d_q : signed(nbits+2 downto 0) := (others => '0'); |
constant c1 : signed(nbits+2 downto 0) := to_signed(1, nbits+3); |
constant c_1 : signed(nbits+2 downto 0) := to_signed(-1, nbits+3); |
begin -- beh1 |
|
process (clk, n_rst) |
begin -- process |
if n_rst = '0' then -- asynchronous reset (active low) |
del1 <= (others => '0'); |
del2 <= (others => '0'); |
dout <= '0'; |
elsif clk'event and clk = '1' then -- rising clock edge |
if clk_ena = '1' then |
del1 <= din - d_q + del1; |
del2 <= din - d_q + del1 - d_q + del2; |
if din - d_q + del1 - d_q + del2 > 0 then |
d_q <= shift_left(c1, nbits); |
dout <= '1'; |
else |
d_q <= shift_left(c_1, nbits); |
dout <= '0'; |
end if; |
end if; |
end if; |
end process; |
|
|
end beh1; |
/trunk/dsm3/makefile
0,0 → 1,22
VHDLS = \ |
dac_dsm3.vhd \ |
dac_dsm3v.vhd \ |
dac_dsm3_top.vhd \ |
dac_tb.vhd \ |
|
|
STD=standard |
#STD=synopsys |
show_spectra: dac_tb.dat |
python show_dac.py |
show_ghw: dac_tb dac_tb.ghw |
gtkwave dac_tb.ghw wzrmb.sav |
dac_tb: ${VHDLS} |
ghdl -a -g --std=93c --ieee=${STD} ${VHDLS} |
ghdl -e --std=93c -fexplicit --ieee=${STD} dac_tb |
dac_tb.dat: dac_tb |
./dac_tb --wave=dac_tb.ghw --stop-time=2000000ns |
dac_tb.ghw: dac_tb |
./dac_tb --wave=dac_tb.ghw --stop-time=2000000ns |
clean: |
rm *.o *.vcd *.ghw *.dat *.cf dac_tb |
/trunk/dsm3/show_dac.py
0,0 → 1,14
import pylab |
#w=load("dac_tb.dat") |
import numpy |
w=numpy.loadtxt("dac_tb.dat") |
t1=[i[1] for i in w]; t1=t1-pylab.mean(t1) |
f1=20.0*pylab.log(0.0001+abs(pylab.fft(t1))) |
pylab.plot(f1) |
pylab.title("Whole spectra of output signal") |
pylab.grid() |
pylab.show() |
pylab.plot(f1[0:1000]) |
pylab.title("First 1000 samples of spectra") |
pylab.grid() |
pylab.show() |
/trunk/README
0,0 → 1,24
This project implements 2nd order DAC implementable in FPGA. |
The converter generates 1-bit digital signal on the dout output. |
You need to connect a simple RC lowpass filter to convert it into |
the analog signal. |
|
There are two implementations: |
dsm2 - allows to obtain higher clock frequency, and therefore |
higher oversampling ratio, but number of rising and falling |
slopes in time unit depends on signal value. Therefore |
you may experience nonlinear distortions if those two slopes |
are not symmetrical. |
dsm3 - The output of the DAC is updated once every three clock pulses. |
If there is a '1' on the DAC output, the sequence '110' is generated |
on the dout output. If there is a '0' on the DAC output, the sequence |
'100' is generated. Therefore we always have one rising slope and one |
falling slope generated in each DAC cycle. |
Unfortunately this implementation accepts lower clock frequencies, |
so the oversampling ratio is lower |
|
To check DAC performance without putting it into real hardware, you can |
run "make" command in the appropriate directory (it requires free tools: |
ghdl, python and pylab). You'll see the spectra of the output signal |
(before low pass filtering) consisting of three sinusoids. |
|