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URL https://opencores.org/ocsvn/simple_agc/simple_agc/trunk

Subversion Repositories simple_agc

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    /simple_agc
    from Rev 1 to Rev 2
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Rev 1 → Rev 2

/trunk/Makefile
0,0 → 1,34
 
SIMCOMPILER = iverilog
SIMULATOR = vvp
VIEWER = gtkwave
 
 
SIMCOMPFLAGS = -v -o
SIMFLAGS = -v
 
 
SRCS = $(wildcard *.v)
TBSRCS = $(filter %_tb.v, $(SRCS))
MODSRCS = $(filter-out %_tb.v %_incl.v, $(SRCS))
VVPS = $(patsubst %.v,%.vvp,$(TBSRCS))
VCDS = $(patsubst %_tb.v,%_tb.vcd,$(TBSRCS))
 
GTKCONF = $(patsubst %_tb.v,%_tb.gtkw,$(TBSRCS))
 
all: disp
 
sim: $(VCDS)
 
$(VVPS): %.vvp: %.v $(MODSRCS)
$(SIMCOMPILER) $(SIMCOMPFLAGS) $(VVPS) $^
 
$(VCDS): %_tb.vcd: %_tb.vvp
$(SIMULATOR) $(SIMFLAGS) $<
disp: $(VCDS)
$(VIEWER) -O /dev/null $(VCDS) $(GTKCONF) &
 
clean:
rm -f $(wildcard *.vvp) $(wildcard *.vcd)
/trunk/agc.v
0,0 → 1,29
module agc(
input wire clk,
input wire rst,
input wire signed [15:0] x_in,
input wire [7:0] a_coef,
input wire [15:0] reference,
output wire signed [15:0] y_out
);
wire [31:0] x_mod;
wire [31:0] ref_rms;
wire signed [32:0] tmp_level;
wire signed [32:0] feedback_level;
reg signed [32:0] zreg;
wire signed [8:0] a_coef_s;
assign a_coef_s = { 1'b0, a_coef};
assign ref_rms = (reference[15:1] * reference[15:1]);
assign x_mod = (y_out * y_out);
assign tmp_level = ($signed(ref_rms - x_mod))>>>18;
assign feedback_level = (tmp_level * a_coef_s) >>> 8;
always @(posedge clk or negedge rst)
if (!rst) zreg <= 'h0;
else zreg <= zreg + feedback_level;
assign y_out = (zreg * x_in) >>>16;
 
endmodule
/trunk/agc_tb.gtkw
0,0 → 1,104
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Wed Dec 27 06:39:13 2017
[*]
[dumpfile] "/home/user1/agc_0.2/agc_tb.vcd"
[dumpfile_mtime] "Wed Dec 27 06:36:14 2017"
[dumpfile_size] 65467369
[savefile] "/home/user1/agc_0.2/agc_tb.gtkw"
[timestart] 0
[size] 1364 715
[pos] -1 -1
*-18.000000 851020 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] agc_tb.
[sst_width] 196
[signals_width] 266
[sst_expanded] 1
[sst_vpaned_height] 189
@28
agc_tb.UUT.clk
@29
agc_tb.UUT.rst
@22
agc_tb.UUT.x_in[15:0]
agc_tb.UUT.y_out[15:0]
@c00024
agc_tb.UUT.ref_rms[31:0]
@28
(0)agc_tb.UUT.ref_rms[31:0]
(1)agc_tb.UUT.ref_rms[31:0]
(2)agc_tb.UUT.ref_rms[31:0]
(3)agc_tb.UUT.ref_rms[31:0]
(4)agc_tb.UUT.ref_rms[31:0]
(5)agc_tb.UUT.ref_rms[31:0]
(6)agc_tb.UUT.ref_rms[31:0]
(7)agc_tb.UUT.ref_rms[31:0]
(8)agc_tb.UUT.ref_rms[31:0]
(9)agc_tb.UUT.ref_rms[31:0]
(10)agc_tb.UUT.ref_rms[31:0]
(11)agc_tb.UUT.ref_rms[31:0]
(12)agc_tb.UUT.ref_rms[31:0]
(13)agc_tb.UUT.ref_rms[31:0]
(14)agc_tb.UUT.ref_rms[31:0]
(15)agc_tb.UUT.ref_rms[31:0]
(16)agc_tb.UUT.ref_rms[31:0]
(17)agc_tb.UUT.ref_rms[31:0]
(18)agc_tb.UUT.ref_rms[31:0]
(19)agc_tb.UUT.ref_rms[31:0]
(20)agc_tb.UUT.ref_rms[31:0]
(21)agc_tb.UUT.ref_rms[31:0]
(22)agc_tb.UUT.ref_rms[31:0]
(23)agc_tb.UUT.ref_rms[31:0]
(24)agc_tb.UUT.ref_rms[31:0]
(25)agc_tb.UUT.ref_rms[31:0]
(26)agc_tb.UUT.ref_rms[31:0]
(27)agc_tb.UUT.ref_rms[31:0]
(28)agc_tb.UUT.ref_rms[31:0]
(29)agc_tb.UUT.ref_rms[31:0]
(30)agc_tb.UUT.ref_rms[31:0]
(31)agc_tb.UUT.ref_rms[31:0]
@1401200
-group_end
@24
agc_tb.UUT.reference[15:0]
@420
agc_tb.UUT.x_mod[31:0]
agc_tb.UUT.tmp_level[32:0]
@22
agc_tb.UUT.a_coef_s[8:0]
@420
agc_tb.UUT.feedback_level[32:0]
agc_tb.UUT.zreg[32:0]
@8420
[color] 1
agc_tb.UUT.x_in[15:0]
@20000
-
-
-
@8420
[color] 7
agc_tb.UUT.y_out[15:0]
@20000
-
-
-
@8420
[color] 2
agc_tb.UUT.zreg[32:0]
@20000
-
-
@8420
[color] 3
agc_tb.UUT.tmp_level[32:0]
@20000
-
-
@8420
agc_tb.UUT.feedback_level[32:0]
@20000
-
-
[pattern_trace] 1
[pattern_trace] 0
/trunk/agc_tb.v
0,0 → 1,96
`timescale 1ns/1ns
 
module agc_tb;
 
reg clk;
reg rst;
wire signed [15:0] x_in;
wire signed [15:0] y_out;
reg [15:0] ref;
reg [7:0] addr;
reg [7:0] sh;
wire [7:0] data;
reg [7:0] a_coef;
reg [15:0] ref_lvl;
always #20 clk = ~clk;
 
 
always @(posedge clk or negedge rst)
if(!rst) addr <= 'h0;
else addr <= addr + 'h1;
 
//always @(posedge clk or negedge rst)
// if(!rst) ref_lvl <= 'h0;
// else if (&addr) ref_lvl <= ref_lvl + 'hf;
 
assign x_in = {$signed(data - 8'h80) , 8'h0};
//assign ref = ref_lvl;
sine_rom SINE(
.addr(addr),
.data(data)
);
 
agc UUT(
.clk(clk),
.rst(rst),
.x_in(x_in >>> sh),
.a_coef(a_coef),
.reference(ref),
.y_out(y_out)
);
 
 
initial begin
clk = 'b0;
rst = 'b0;
sh = 'h1;
ref = 'h3fff;
a_coef = 'h3f;
#20 rst = 'b1;
#100000
sh = 'h2;
#200000
sh = 'h1;
#100000
sh = 'h0;
#100000
sh = 'h2;
#250000
sh = 'h3;
#250000
sh = 'h0;
#250000
sh = 'h2;
#10000000
$write("Simulation has finished");
$finish;
end
 
initial begin
$dumpfile("agc_tb.vcd");
$dumpvars(0,agc_tb);
end
 
endmodule
 
 
module sine_rom(
input [7:0] addr,
output [7:0] data
);
 
reg [7:0] mem [0:255];
initial
$readmemh("sine.txt", mem);
 
assign data = mem[addr];
endmodule
/trunk/sine.txt
0,0 → 1,256
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