URL
https://opencores.org/ocsvn/simu_mem/simu_mem/trunk
Subversion Repositories simu_mem
Compare Revisions
- This comparison shows the changes necessary to convert path
/simu_mem/trunk/sim/rtl_sim
- from Rev 3 to Rev 5
- ↔ Reverse comparison
Rev 3 → Rev 5
/bin/modelsim.inc
0,0 → 1,13
function check_executable { |
if [ ! -x $1 ]; then |
echo "$1 does not exist or is not executable." |
exit 0 |
fi |
} |
|
function map { |
if [ ! -d ../out/$1 ] ; then |
vlib ../out/$1 |
vmap $1 $2 |
fi; |
} |
bin/modelsim.inc
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: bin/sim.sh
===================================================================
--- bin/sim.sh (nonexistent)
+++ bin/sim.sh (revision 5)
@@ -0,0 +1,73 @@
+#!/bin/bash
+#
+# This script runs RTL simulation.
+# Right now only Modelsim is supported.
+#
+# Author: Michael Geng
+#
+
+# Number of clock cycles you want to run the simulations
+N_simulation_cycles=100
+
+# data bus width
+D_width=36
+
+# address bus width
+A_width=21
+
+. modelsim.inc
+
+if [ -z $MODEL_SIM ]; then
+ echo "The environment variable MODEL_SIM must point to your Modelsim installation."
+ exit 0
+fi
+
+vlib=$MODEL_SIM/win32pe/vlib
+vcom=$MODEL_SIM/win32pe/vcom
+vsim=$MODEL_SIM/win32pe/vsim
+
+for tool in $vlib $vcom $vsim
+do
+ check_executable $tool
+done
+
+touch modelsim.ini
+
+mkdir -p ../out
+
+# map libraries
+map std "$MODEL_SIM/std"
+map ieee "$MODEL_SIM/ieee"
+map verilog "$MODEL_SIM/verilog"
+map RAM ../out/RAM
+map misc ../out/misc
+map samsung ../out/samsung
+map test_zbt ../out/test_zbt
+
+# compile
+vcom -work ../out/misc ../../../bench/vhdl/misc/math_pkg.vhd
+
+vlog +define+hc25 -work ../out/samsung ../../../bench/verilog/samsung/k7n643645m_R03.v
+
+vcom -work ../out/RAM ../../../rtl/vhdl/linked_list_mem_pkg.vhd
+vcom -work ../out/RAM ../../../rtl/vhdl/ZBT_RAM_pkg.vhd
+vcom -work ../out/RAM ../../../rtl/vhdl/ZBT_RAM.vhd
+
+vcom -work ../out/test_zbt ../../../bench/vhdl/zbt_ram/patgen_pkg.vhd
+vcom -work ../out/test_zbt ../../../bench/vhdl/zbt_ram/patgen_entity.vhd
+vcom -work ../out/test_zbt ../../../bench/vhdl/zbt_ram/patgen_arch_random.vhd
+vcom -work ../out/test_zbt ../../../bench/vhdl/zbt_ram/patgen_arch_deterministic.vhd
+vcom -work ../out/test_zbt ../../../bench/vhdl/zbt_ram/testbench.vhd
+vcom -work ../out/test_zbt ../../../bench/vhdl/zbt_ram/testbench_random_conf.vhd
+vcom -work ../out/test_zbt ../../../bench/vhdl/zbt_ram/testbench_deterministic_conf.vhd
+
+mkdir -p ../log
+
+# simulate
+echo "Simulate with deterministic pattern"
+vsim -l ../log/zbt_deterministic.out -c -t 100ps -GD_width=$D_width -GA_width=$A_width \
+ -GN_simulation_cycles=$N_simulation_cycles -do "run -all ; quit ;" test_zbt.deterministic_conf
+
+echo "Simulate with random pattern"
+vsim -l ../log/zbt_random.out -c -t 100ps -GD_width=$D_width -GA_width=$A_width \
+ -GN_simulation_cycles=$N_simulation_cycles -do "run -all ; quit ;" test_zbt.random_conf
bin/sim.sh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property
Index: bin/clean.sh
===================================================================
--- bin/clean.sh (nonexistent)
+++ bin/clean.sh (revision 5)
@@ -0,0 +1,4 @@
+#!/bin/bash
+rm -r ../out
+rm -r ../log
+rm modelsim.ini
bin/clean.sh
Property changes :
Added: svn:executable
## -0,0 +1 ##
+*
\ No newline at end of property